RS FLIP FLOP BASIC OPERATION. INEL 4207 Digital Electronics - M. Toledo

Transcription

1 RS FLIP FLOP BASIC OPERATION INEL 427 Digital Electronics - M. Toledo

2 Figure 6. A 2 M+N -bit memory chip organized as an array of 2 M rows 2 N columns.

3

4 Figure 6. (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch.

5 Figure 6.2

6 Figure 6.3 (a) The set/reset (SR) flip-flop and (b) its truth table.

7 Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

8 Assume Q=, Q = Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

9 Assume Q=, Q = Clock and S go high Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

10 Assume Q=, Q = Clock and S go high Q is pulled down Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

11 Assume Q=, Q = Clock and S go high Q is pulled down voltage at Q increases Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

12 Assume Q=, Q = Clock and S go high Q is pulled down voltage at Q increases Q reaches critical point Vdd/2 Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

13 Assume Q=, Q = Clock and S go high Q is pulled down voltage at Q increases Q reaches critical point Q reaches critical point Vdd/2 Vdd/2 Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

14 Assume Q=, Q = Clock and S go high Q is pulled down voltage at Q increases Q reaches critical point Q reaches critical point S is be removed Vdd/2 - ΔV Vdd/2 + ΔV Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

15 Assume Q=, Q = Clock and S go high Q is pulled down voltage at Q increases Q reaches critical point Q reaches critical point S is be removed Regenerative action restore levels Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

16 Assume Q=, Q = Clock and S go high Q is pulled down voltage at Q increases Q reaches critical point Q reaches critical point S is be removed Regenerative action restore levels FF is SET Fig. 6.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by ϕ. -

17 EXAMPLE The CMOS SR flip-flop in Fig. 6.4 is fabricated in a.8-µm process for which µncox = 4 µpcox = 3 µa/v 2, Vtn = Vtp =.5V, and VDD =.8V. The inverters have (W/L)n =.27µm/.8µm and (W/L)p = 4 (W/L)n. The four NMOS transistors in the set-reset circuit have equal W/L ratios. (a) Determine the minimum value required for this ratio to ensure that the flipflop will switch. (b) Also, determine the minimum width the set pulse must have for the case in which the W/L ratio of each of the four transistors in the set-reset circuit is selected at twice the minimum value found in (a). Assume that the total capacitance at each of the Q and Q nodes and ground is 2fF.

18 EXAMPLE µncox = 4 µpcox = 3 µa/v 2, Vtn = Vtp =.5V, and VDD =.8V. The inverters have (W/L)n =.27µm/.8µm and (W/ L)p = 4 (W/L)n. (a) Determine the minimum value of (W/L)5,6,7,8 required to ensure that the flip-flop will switch. Solution: Assume Q = and that you want to Set the flip flop Replace Q 5 and Q 6 with an equivalent transistor Q eq for which (W/L) eq = (W/L) 5,6 /2 Assume that v Q does not change, i.e. remains fixed at V Observe that Q 2 operates in triode mode when V Q = V DD /2 =.9V because v SD,2 =.9V < v SG2 V tp =.8V.5V =.3V. Likewise, Q eq operates in triode mode. Equate i D,2 and i D,eq µ n C ox W 2 L eq 2(.3V ).9V (.9V ) 2 = µ n C ox µm (4) 2(.3V ).9V (.9V ) 2.8µm Simplify to obtain W L eq = 2 W L 5,6,7,8 =.27µm.8µm

19 EXAMPLE (b) Also, determine the minimum width the set pulse must have for the case in which the W/L ratio of each of the four transistors in the set-reset circuit is selected at twice the minimum value found in (a). Assume that the total capacitance at each of the Q and Q nodes and ground is 2fF. Solution: Set (W/L)5 = (W/L)6 = (W/L)7 = (W/L)8 =.8um/.8um. Set ts = tphl + tplh where tphl is the time it takes for vq to go from VDD to VDD/2 and tplh is the time it takes for vq to go from V to VDD/2 To find tphl, use ic = id,eq - id2. At t =, vq = VDD and Q2 is off, Qeq is saturated and ic = 76.5uA. At t = tphl, vq = VDD/2, id2 = uA, ideq = 688.5uA and ic2 = uA. So ic,ave = 552.4uA and tphl = (2fF)(.9V)/552 ua = 32.6ps. To find tplh, you can use the formula from ch. 4 that use α to get tplh = 49.5ps. Tmin = tphl + tplh = 82.ps

20 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips.

21 Figure 6.8 A block diagram representation of the D flip-flop.

22 Figure 6.9 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase non-overlapping clock whose waveforms are shown in (b).

23 Figure 6. (a) A master slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase non-overlapping clock required.