CSEE 3827: Fundamentals of Computer Systems SOLUTIONS

Transcription

1 CSEE 3827: Fundamentals of Computer Systems Midterm Eam March 9, 2 SOLUTIONS Read all of the following information before starting the eam: Be sure to write your name on each page of the eam. Use the eam itself for your solutions (no blue books or spare sheets of paper). You may use the backside of pages if you need more space. Show your work in order to earn partial credit. You may use your tetbook and class notes, but absolutely no electronic devices (laptops, cell phones, etc.) Good luck! Problem Point Value Points Earned Total 5

2 . (2 points) Salt and pepper. (a) (2 points) Prove algebraically that BC + AB + AB = B. BC + AB + AB B(C + A + A) B(C + ) B() B (b) (4 points) raw a schematic for a minimal circuit that uses only and, or, and not gates that performs the two s complement operation on a four bit input value. Let the input be X 3: and the output be Y 3:. X 3 X 2 X X Y 3 Y 2 Y Y Y 3 = X 3 X 2 + X 3 X + X 3 X + X 3 X 2 X X Y 2 = X 2 X X + X X 2 + X X 2 Y = X X + X X Y = X Y3: X X Y2: X X Y: X X X3 X2 X3 X2 X3 X2 CSEE Midterm Eam Page 2 of 8

3 (c) (2 points) Eamine the sequential circuit below. First, give a complete truth table, then describe conceptually what the circuit does. X Z Y X Y Z Z prev (hold) (reset) (set) (set) This is an RS latch, but instead of instability when both inputs are, this latch sets. (d) (4 points) esign a Moore machine robot controller which causes a robot to wave (output W = ) in 4% of the time (I.e,, in 4% of its states, any 4% will do) Implement this controller using flip-flops. W CSEE Midterm Eam Page 3 of 8

4 2. ( points) esign a 32-bit ALU (arithmetic logic unit) which computes either +,,, of two 32-bit values A and B putting the result on 32-bit output C. You may assume the presence of eisting a 32-bit adder, subtractor, multiplier, and divider, and you may incorporate them in your design as black boes. The particular operation is controlled by an additional two bit input S, where NB: In addition to the arithmetic modules, you may incorporate mues, decoders, and other standard components as you find helpful. if S =, C = A + B if S =, C = A B if S =, C = A B if S =, C = A B (a) raw a schematic for your ALU design. (b) Give an epression for the propagation delay (T P ALU ) and contamination delay (T C ALU ) of your ALU, in terms of the propagation and contamination delays of the sub-modules. For eample, T P + is the propagation delay of the adder, and T C MUX is the contamination delay of a mu. A 32 B * / S 2 32 C T P ALU = ma(t P +, T P, T P, T P ) + T P MUX T C ALU = min(t C +, T C, T C, T C ) + T C MUX CSEE Midterm Eam Page 4 of 8

5 3. (8 points) Eamine the circuit below. Note that these flip-flops are negative, or falling, edge triggered. C X Y Z (a) Complete the following timing diagram. You may assume wires and gates have zero delay (i.e., all transitions are instantaneous), and that at the start X = Y = Z =. C X Y Z (b) escribe conceptually what this circuit does. This is a 3-bit up-counter. CSEE Midterm Eam Page 5 of 8

6 4. ( points) Use flip-flops and basic combinational gates (AN, OR, NOT) to design the following counter/pseudorandom number generator. The circuit has a CLK and and one control input. It provides a three bit output indicating the numeric output N 2:. When =, the circuit should operate a binary up-counter. Otherwise, it should operate as a pseudorandom number generator according to the following function table. NB: While your design must use only the primitive elements listed above, it need not be minimal. Pre State Net State Binary Pseudorandom Up-Counter No. Gen. ( = ) ( = ) (unlabeled edges transition on ) Use 8 flipflops, with a one hot state encoding (i.e., state i i ) Net state logic = = = = = = = = Output logic N 2 = N = N = CSEE Midterm Eam Page 6 of 8

7 5. ( points) Give a state transition diagram for a Message Transmission Controller Mealy Machine. Messages are broken into four packets for transmission, so sending a message amounts to sending packet, packet, packet 2, and packet 3. The sender must receive an acknowlegement of packet i before transmitting packet i +. NB: You need only provide the state transition diagram, no implementation necessary. The Message Transmission controller has the following interface: Inputs: MSG SEN: bit signal that initiates the transmission of the four packets that comprise the message PKT ACK: bit signal acknowledging receipt of the previous packet Outputs: PKT SEN: bit signal that initiates the transmission of a packet PKT I: 2 bits indicating which packet is to be MSG_SEN /, ACK /, ACK /, ACK /, ACK /, MSG_SEN /, 2 3 ACK /, ACK /, ACK /, 4 ACK /, (output code: PKT_SEN, PKT_I) CSEE Midterm Eam Page 7 of 8

8 (Scratch space.) CSEE Midterm Eam Page 8 of 8