CMOS Logic Circuit Design Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計
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1 CMOS Logic Circuit Design Link( リンク ): センター教官講義ノートの下 CMOS 論理回路設計 Special-Purpose Digital Circuits Buffer Circuits Path-Selector Circuits Information-Storing Circuits Trigger Circuits Multi-Vibrator Circuits Voltage-Generator Circuits Mattausch, CMOS Design, H20/5/2 1
2 Necessary Functions other than Logic Operations 1) Transmission of signals over long interconnection lines or to many receivers - Buffer (inverting, non-inverting, tri-state) 2) Selection of an interconnection for a Signal according to a condition - Selector (multiplexer, demultiplexer) 3) Storing an information for some time - Flip-flop, latch 4) Removing Noise from a Signal - Trigger circuits 5) Generation of Synchronous or Asynchronous Control Signal - Multi-vibrator circuits (a-stable, bi-stable, mono-stable) 6) Generation of other Voltages than VDD or VSS - Voltage generator circuits CMOS logic circuits do contain more than only logic gates. Mattausch, CMOS Design, H20/5/2 2
3 Buffer Circuits - Increasing the driving capability of a logic signal for large load capacities - Conventional non-inverting buffers - Inverting buffers - Tri-state buffers Mattausch, CMOS Design, H20/5/2 3
4 Reduction of Logic-Gate Fan-Out with a Buffer NAND-gate with fan-out = k, fan-in = m NAND-gate with fan-out = 1, fan-in = m m-1 m m-1 m k Non-inverting Buffer k Delay without buffer tdf NAND = m (m t fin + k t t = m t + k t, fex dr, NAND rin rex ) Delay with buffer t df, NAND = m (m t fin + t fex ) + t t = m t + t + t dr, NAND rin rex buffer buffer The delay of a circuit with large fan-out (i. e. large output load) can be reduced with a buffer, if (k-1) t rex > t buffer is valid. Mattausch, CMOS Design, H20/5/2 4
5 Construction of Non-Inverting CMOS Buffers V in V out Optimum choice of A and N C load VSS A ni buffer C = C load in1 1 2 N V in A 0 W p W n A 1 W p W n A 2N 2 W p W n A 2N 1 W p W n I 1 I 2 I 2N-1 I 2N VSS V out C load N ni buffer = int 1 2 C ln C load (C in1 is the input capacity of the 1 st inverter) in1 Non-inverting buffers have even number of inverters. Each stage has a factor A ni-buffer (C load,c in ) larger driving capability. Mattausch, CMOS Design, H20/5/2 5
6 Construction of Inverting CMOS Buffers V in V out Optimum Choice of A and N C load VSS A i buffer C = C load in1 1 2 N + 1 V in A 0 W p W n A 1 W p W n A 2 W p W n A 2N 1 W p W n A 2N W p W n I 1 I 2 I 3 I 2N I 2N+1 VSS V out C load N = int C ln C 1 load 1 i buffer 2 2 in1 (C in1 is the input capacity of the 1 st inverter) Inverting buffers use an odd number of cascaded inverters. Each stage has again A i-buffer (C load,c in ) larger driving capability. Mattausch, CMOS Design, H20/5/2 6
7 Tri-State Inverter Symbol En CMOS-Circuit Implementation In Out VDD In Out Truth Table En In Out 0 0 floating 0 1 floating VSS En A tri-state inverter has an additional high-impedance or floating output state selected with an enable signal. It can be built with a conventional inverter and a transmission gate. Mattausch, CMOS Design, H20/5/2 7
8 Tri-State Buffers non-inverting tri-state buffer En CMOS-Circuit Implementation VDD In Out inverting tri-state buffer In I 1 I 2 I N-1 I N Out En In Out En VSS A tri-state buffer combines high driving capability for a large load capacity C load and the possibility of a floating output. Mattausch, CMOS Design, H20/5/2 8
9 Path-Selector Circuits - Multiplexer- and Demultiplexer Principles - Implementation with Transmission Gates - Series Connection of Transmission Gates - Implementation with Tri-State Inverters or Tri-State Buffers Mattausch, CMOS Design, H20/5/2 9
10 Multiplexer and Demultiplexer Principles between ln(n) and N Control/Selector Lines between ln(n) and N Control/Selector Lines N Data Input Lines Multiplexer (MUX) One Selected Data Output One Data Input Demultiplexer (DEMUX) N Possible 0utput Lines N N Conditional signal-path selection is performed with multiplexer- or demultiplexer circuits. Mattausch, CMOS Design, H20/5/2 10
11 Multiplexer Realization with Transmission Gates In Transmission Gates Symbols En En Out In Out 4-Input Multiplexer Minimum Transmission Gates En 1 En 2 En 3 En 4 In 1 In 2 Out In 3 En Circuits En In 4 Minimum Select Signals En 1 En 2 In Out In Out In 1 In 2 In 3 Out In 4 Path-selector realization is easiest by transmission gates. Mattausch, CMOS Design, H20/5/2 11
12 Series Connection of Transmission Gates Series of N transmission gates driving a load Delay model for a series of N transmission gates Delay equation as a function of N transmission gates t PS,hl t PS,lh ( R n R p )C ( load ) N ( R n R p )C ( inn + C inp ) N 2 A series connection of N transmission gates represents an RC-chain. Therefore, its delay time increases with N 2. Mattausch, CMOS Design, H20/5/2 12
13 MUX/DEMUX Realization with Tri-State Buffers Multiplexer Demultiplexer En 1 En 2 En 3 En N En N En 3 En 2 En 1 In 1 Out 1 In 2 Out 2 In 3 Out In Out 3 In N Out N With tri-state buffers the delay problem of signal-path selectors is solved at the cost of larger integration-area. Mattausch, CMOS Design, H20/5/2 13
14 Information-Storing Circuits - Stabilizing-Feedback Principle - Set-Reset Flip-Flop - Clocked Flip-Flops Level Sensitive Flip-Flops Edge-Triggered Flip-Flops Flip-Flop Timing Mattausch, CMOS Design, H20/5/2 14
15 Stabilizing-Feedback Principle of Data Storage Stabilizing inverterfeedback coupling Resulting stable circuit states Stable States one zero By feeding back the identical signal to a circuit node, stable circuit states result, which are usable for data storage. Mattausch, CMOS Design, H20/5/2 15
16 Set-Reset (SR) Flip-Flop Circuit diagram (constructed with NAND gates) Logic Symbol Truth table S R S SR Flip-Flop R S R Set-reset flip-flops extend the stabilizing feedback principle by a method for external modification of the stored data. Mattausch, CMOS Design, H20/5/2 16
17 Level-Sensitive Data (D) Flip-Flop Circuit diagram (constructed with NAND gates) Logic Symbol D S D CLK SR Flip-Flop D Flip-Flop R CLK The level-sensitive data (D) flip-flop extends the SR flip-flop with additional circuitry for clock-controlled writing of data. Mattausch, CMOS Design, H20/5/2 17
18 Latch: Transmission-Gate Version of D Flip-Flop Circuit diagram of a latch (data flip-flop constructed with inverters and transmission gates) CLK D The simplest construction of level-sensitive data (D) flip-flops has 2 inverters and 2 transmission gates and is called latch. Mattausch, CMOS Design, H20/5/2 18
19 Edge-Triggered data (D) Flip-Flop Circuit diagram of a D flip-flop into which data is written at the positive edge (low-high) change of the clock (constructed with 2 latches) CLK D Master Latch Slave Latch The edge-triggered D flip-flop has 2 latches. Data transfer to the slave latch occurs only at transition edges of the clock. Mattausch, CMOS Design, H20/5/2 19
20 Timing of Flip-Flops for Safe Data Writing Volt VDD positive edge of the clock signal D CLK Set-up time t s hold time t h VSS Minimum stable data time t s +t h Time The safe operation of a flip-flop requires stable data signals for a minimum time around the clock edge, which determines data transfer into the storage part of the flip-flop. Mattausch, CMOS Design, H20/5/2 20
21 Trigger Circuits - Removal Possibilities of Signal Noise - Schmitt-Trigger Circuit Mattausch, CMOS Design, H20/5/2 21
22 Signal Noise and Removal Possibilities Noise-Removal Circuit Input Noise-Removal Circuit Output VDD VSS VDD VSS High-Switching Point V SPH Low-Switching Point V SPL Time Inverting Removal Circuit Assumed Time Output Voltage Desired Switching-Point Characteristic of Circuit VDD VSS VSS V SPL V SPH Input Voltage VDD Noise can be removed from a signal with a circuit who has different switching points for low-high and high-low transition. Mattausch, CMOS Design, H20/5/2 22
23 Schmitt-Trigger Circuit Schmitt-Trigger Symbol VDD M5 M6 Design of n-mos Transistors M1 and M2 determines the High-Switching Point β 1 VDD VSPH β2 VSS+ VSPH V TH,n 2 CMOS Circuit In M4 M3 M1 M2 VSS VDD Out Design of p-mos Transistors M5 and M6 determines the Low-Switching Point β 5 β 6 VSS+ V SPL VDD V SPL V TH, p 2 VSS The CMOS inverter circuit can be easily modified to obtain an inverting Schmitt-trigger circuit to reduce input-signal noise. Mattausch, CMOS Design, H20/5/2 23
24 Multi-Vibrator Circuits - Destabilizing-Feedback Principle - A-Stable Multi-Vibrator or Oscillator - Bi-Stable Multi-Vibrator or Flip-Flop (see Part on Information-Storing Circuits) - Mono-Stable Multi-Vibrator Mattausch, CMOS Design, H20/5/2 24
25 Destabilizing Feedback: Oscillator Circuits Destabilizing inverterfeedback coupling Resulting unstable (oscillating) signals at circuit nodes i VDD 1 2 VSS 3 Time By feeding back the inverted signal to a circuit node, an unstable state is occurs, which is used for oscillator circuits. Mattausch, CMOS Design, H20/5/2 25
26 Ring-Oscillator Circuit with N Stages Ring-Oscillator constructed with an odd number N of inverters Obtained oscillator frequency V osc f osc 1 ( ) N t IHL + t ILH CMOS oscillators can be constructed with an odd number of inverters. The oscillator frequency f osc is determined by inverter low-high/high-low transitions and inverter number. Mattausch, CMOS Design, H20/5/2 26
27 Mono-Stable Multi-Vibrator Mono-stable multi-vibrator example constructed with NOR and inverter Generation of long pulse with fixed length by short trigger pulse at input V in VDD R C V 1 V 2 V out V out V 2 t pulse t pulse RC ln VDD VDD V SP,I V 1 V in Time A mono-stable multi-vibrator is a circuit with delayed stable feedback. Thus pulses with fixed length can be generated. Mattausch, CMOS Design, H20/5/2 27
28 Voltage-Generator Circuits Mattausch, CMOS Design, H20/5/2 28
29 Simple Generator for Voltages >VDD and <VSS High-voltage generator Transient output of the high voltage generator V out 2VDD 2V TH, n Low-voltage generator V out VDD+ 2V TH, n Voltage-generator circuits are applied, if the circuits in the CMOS chip need other supply voltages than VDD and VSS. Mattausch, CMOS Design, H20/5/2 29
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