l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on.

Transcription

1 CS211 Computer Architecture l Topics Digital Logic l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Class Checkpoint l What have discussed up until now & why: l C Programming language l More low-level then Java. l Better idea about what s really going on. l Covered data representation l Computers manipulate data. How is this data stored and manipulated? l Covered Machine-Level representation of programs (assembly lanaguage - x86) l Computers don t work on C code (or Java). Need instructions closer to hardware. l What s next? Processor Design how does machine instructions actually make the processor work? Figures & Tables borrowed from:! But first l Before we go into processor design, we re going to cover some topics in Digital Logic. l Book covers this only sparingly, we re going to go into a bit more detail. l Specifically: l Transistors l Logic gates l Combinational & Sequential Circuits l Flip-Flops l Memory Transistor: Building Block of Computers l Microprocessors contain millions of transistors l Intel Pentium 4 (2000): 48 million l IBM PowerPC 750FX (2002): 38 million l IBM/Apple PowerPC G5 (2003): 58 million l Logically, each transistor acts as a switch l Combined to implement logic functions l AND, OR, NOT l Combined to build higher-level structures l Adder, multiplexer, decoder, register, l Combined to build processor 1

2 Simple Switch Circuit n-type MOS Transistor l Switch open: l No current through circuit l Light is off l V out is +2.9V l Switch closed: l Short circuit across switch l Current flows l Light is on l V out is 0V Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage. l MOS = Metal Oxide Semiconductor l two types: n-type and p-type l n-type l when Gate has positive voltage, short circuit between #1 and #2 (switch closed) l when Gate has zero voltage, open circuit between #1 and #2 (switch open) Terminal #2 must be connected to GND (0V). Gate = 1 Gate = 0 p-type MOS Transistor l p-type is complementary to n-type l when Gate has positive voltage, open circuit between #1 and #2 (switch open) l when Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Inverter (NOT Gate) Truth table In Out In Out Gate = 0 0 V 2.9 V 2.9 V 0 V Terminal #1 must be connected to +2.9V. 2

3 NOR Gate OR Gate A B C Note: Serial structure on top, parallel on bottom. A B C Add inverter to NOR. NAND Gate (NOT(AND)) AND Gate A B C Note: Parallel structure on top, serial on bottom. A B C Add inverter to NAND. 3

4 Basic Logic Gates Symbols XOR: truth table A^B A B A XOR B + XOR A O + B - - A^B= A & B + A&B DeMorgan's Law l NOT (A and B) = NOT (A) OR NOT (B) l NOT (A OR B) = NOT(A) AND NOT (B) A BB NOT(A AND B) NOT (A) NOT (B) NOT(A) OR NOT(B) DeMorgan's Law l Converting AND to OR (with some help from NOT) l Consider the following gate: To convert AND to OR (or vice versa), invert inputs and output. A B A B A B A B Same as A OR B 4

5 More than 2 Inputs? l AND/OR can take any number of inputs. l AND = 1 if all inputs are 1. l OR = 1 if any input is 1. l Similar for NAND/NOR. l Can implement with multiple two-input gates, or with single CMOS circuit. Building Functions from Logic Gates l Combinational Logic Circuit l output depends only on the current inputs l stateless l Sequential Logic Circuit l output depends on the sequence of inputs (past and present) l stores information (state) from past inputs l We'll first look at some useful combinational circuits, then show how to use sequential circuits to store information. Half adder l A half adder is used to add just two bits. l The result consists of two bits: a sum (the right bit) and a carry out (the left bit) S l Here is the circuit and its block symbol X Y CS = = = = 10 C Full Adder l Add two bits and carry-in, produce one-bit sum and carry-out. A B C in S C out

6 Four-bit Adder (carry-ripple adder) Carry Save adder l Compute Sum and Carry independently l l l l Disadvantage: Delay through N-1 Stages l Then add S + C 000 l 101- l l 1010 Carry Save adder l Delay reduced compared to Carry ripple adder l Add 3 Numbers and Produce two numbers S and C X: Y: Z: C: l Final result is S + shifted carry X: Y: Z: S: C: Sum: X: Y: Z: S: Carry Save Adder Design X Y Z CSA n+1 n C=carry S=sum + X X n-1 Y n-1 Z n-1 n-2 Y n-2 X Z n-2 0 Y 0 Z 0 FA FA FA C n S C n-1 C 1 n-1 S n-2 S 0 N Bit Carry Save Adder Block C 0 =0 6

7 Decoder l n inputs, 2 n outputs l exactly one output is 1 for each possible input pattern Decoder l n inputs, 2 n outputs l exactly one output is 1 for each 0 possible input pattern 2-bit decoder 2-bit decoder Selecting Memory Multiplexer (MUX) A0.. A7 256 x 8 RAM 256 x 8 RAM 256 x 8 RAM 256 x 8 RAM l n-bit selector and 2 n inputs, one output l output equals one of the inputs, depending on selector A8 A9 2 to 4 decoder 4-to-1 MUX 7

8 Circuit Design Converting Truth Table to Boolean Expression l Designing circuits is a process 1. Have a good idea. What kind of circuit might be useful? 2. Derive a truth table for this circuit. 3. Derive a Boolean expression for the truth table. 4. Build a circuit given the Boolean expression l l Building the circuit involves mapping the Boolean expression to actual gates. This part is easy. Deriving the Boolean expression is easy. Deriving a good one is tricky. l Given a circuit, isolate that rows in which the output of the circuit should be true. Converting Truth Table to Boolean Expression Converting Truth Table to Boolean Expression l Given a circuit, isolate that rows in which the output of the circuit should be true. l A product term that contains exactly one instance of every variable is called a minterm. l Given the expressions for each row, build a larger Boolean expression for the entire table. l This is a sum-of-products (SOP) form. 8

9 Converting Truth Table to Boolean Expression First Approach: Algebraic l Simply use the rules of Boolean logic l Finally build the circuit. l Problem: SOP forms are often not minimal. l Solution: Make it minimal. We ll go over two ways. The Result Karnaugh Maps or K-Maps l K-maps are a graphical technique to view minterms and how they relate. l The map is a diagram made up of squares, with each square representing a single minterm. l Minterms resulting in a 1 are marked as 1, all others are marked 0 9

10 2 Variable K-Map 2 Variable K-Map 2 Variable K-Map Finding Commonality

11 Finding the best solution Simplify Example l Grouping become simplified products. l Both are correct. A+B is preferred. Simplify Example 3 Variable K-Maps C l Note in higher maps, several variables occupy a given axis l The sequence of 1s and 0s follow a Gray Code Sequence. B 11

12 3 Variable K-Maps 3 Variable K-Maps C B 3 Variable K-Maps 3 Variable K-Maps 12

13 3 Variable K-Maps Back to our earlier example.. l The K-map and the algebraic produce the same result. Up up and let s D keep going Few more examples D A C B A B C 13

14 Few more examples D A B C 14