2003 IC/CAD Contest Problem 5: Clock Tree Optimization for Useful Skew

Transcription

1 2003 IC/CAD Contest Problem 5: Clock Tree Optimization for Useful Skew Source: Global UniChip Corp. February 11, 2003, revised on March 21, 2003 & April 22, Introduction There are two approaches to resolve the timing violation of a critical path. One is to apply logic optimization technique to the path for reducing its path delay, and the other is to adjust clock arrival times of the starting flip-flop and ending flip-flop of that path such that the starting flip-flop can launch data earlier or the ending flip-flop can latch data later to compensate the timing slack due to timing violation. For those critical paths whose logic levels are too high and are difficult to be optimized, the later technique would be much effective. The clock latency of a flip-flop s clock pin is the path delay starting from clock root through the distribution cells, and ending at the clock pin (leaf pin). In other words, the arrival time of a flip-flop s clock pin is its clock latency. The clock latency of a clock tree is the maximum clock latency from clock root to any leaf pin. The clock skew of two flip-flops is the difference of their clock latencies, and the clock skew of a clock tree is the maximum difference among the clock latencies of the leaf pins. As an example shown in Fig. 1, the arrival times (clock latencies) of F1.CK, F2.CK, and F3.CK all are 2ns, and thus the clock latency of clock tree CLK is 2ns, where for example F1.CK stands for CK pin of flip-flop F1. The clock skew of F1.CK and F2.CK is 0ns, and the clock skew of clock tree CLK is 0ns as well. For another example shown in Fig. 3, the clock latencies of F1.CK, F2.CK, and F3.CK are 1.9ns, 2.4ns, and 2ns respectively, and the clock latency of clock tree CLK is 2.4ns. The clock skew of F1.CK and F2.CK is 0.5ns (2.4ns 1.9ns) that is also the clock skew of CLK. Cycle delay Tck12=10ns Tck23=10ns from CK to CK Tp12=t11+t12=10.4ns Tp23=t21+t22=9.5ns Data path delay Ts2 = 0.1ns Ts3 = 0.1ns CLK F1 F2 F3 D Q D Q D Q t11 CK CK CK Ta1_CK = 2ns t12 Ts2 Ts3 t21 t22 Ta2_CK = 2ns Ta3_CK = 2ns Fig 1. A design with timing violations 1

2 t11: cell delay from F1.CK to F1.Q t12: path delay from F1.Q to F2.D Tp12: path delay from F1.CK to F2.D (t11+t12) Ta1_CK: arrival time of F1.CK Tck12: the cycle delay from F1.CK to F2.CK Ts2: setup time of F2.D w.r.t. F2.CK Tr2_D: the required time of F2.D Ta2_D: the arrival time of F2.D CLK F1.CK F2.CK Clock rise 2ns Ta1_CK Ta2_CK Clock Cycle m Clock Cycle m+1 Clock cycle =10ns 2ns Tck12 = 10ns Next clock rise F2.D Tr2_D = 11.9ns Ts2= 0.1ns Data Ready Tp12 = 10.4ns Ta2_D = 12.4ns Slack2 = -0.5ns Fig 2. Timing diagram of Fig. 1 In Fig 1, the clock latency and clock skew of CLK are 2ns and 0ns, respectively. Assume that the clock cycle time is 10ns, both of Ts2 and Ts3 are 0.1ns, and the data path delays of Tp12 and Tp23 are 10.4ns and 9.5ns, respectively. By referring to the timing diagram shown in Fig. 2, the data launched at F1 (F2) at clock cycle m is to be captured at F2 (F3) at clock cycle m+1. Thus, the data required time of F2.D and F3.D are as follows. Tr2_D = (Clock cycle time) + (F2.CK clock latency) (F2.D setup time) = 10ns + 2ns 0.1ns = 11.9ns Tr3_D = (Clock cycle time) + (F3.CK clock latency) (F3.D setup time) = 10ns + 2ns 0.1ns = 11.9ns And, the data arrival times are Ta2_D = (F1.CK clock latency) + (F1.CK to F2.D path delay) = 2ns ns = 12.4ns Ta3_D = (F2.CK clock latency) + (F2.CK to F3.D path delay) = 2ns + 9.5ns = 11.5ns Thus, we can find the timing slacks are Slack2 = Tr2_D Ta2_D = -0.5ns Negative timing slack (setup time) Slack3 = Tr3_D Ta3_D = 0.4ns Meet timing requirement. There is 0.5ns negative timing slack in the critical path from F1.CK to F2.D. 2

3 Cycle delay Tck12=10.5ns Tck23=9.6ns from CK to CK Tp12=10.4ns Tp23=9.5ns Data path delay Ts2 = 0.1ns Ts3 = 0.1ns D Q D Q D Q F1 F2 F3 CK CK CK Ta1_CK = 1.9ns 2.4ns 2.0ns Fig 3. A design without timing violation Clock rise Clock Cycle m Clock Cycle m+1 Clock cycle =10ns Next clock rise CLK F1.CK F2.CK 1.9ns Tck12=10.5ns 2.4ns F2.D Tr2_D=12.3ns Tp12=10.4ns Ta2_D=12.3ns Data Ready Ts2= 0.1ns Fig 4. Timing diagram of Fig. 3 Slack2 = 0ns To resolve the timing violation above, one can adjust the clock latencies of F1 and F2, and let F1 launches data earlier and F2 captures data later to compensate the negative timing slack. Fig 3 demonstrates an example of fixing the timing violation, in which the data required times of F2.D and F3.D are Tr2_D = (Clock cycle time) + (F2.CK clock latency) (F2.D setup time) = 10ns + 2.4ns 0.1ns = 12.3ns Tr3_D = (Clock cycle time) + (F3.CK clock latency) (F3.D setup time) = 10ns + 2ns 0.1ns = 11.9ns And, the data arrival times are Ta2_D = (F1.CK clock latency) + (F1.CK to F2.D path delay) = 1.9ns ns = 12.3ns 3

4 Ta3_D = (F2.CK clock latency) + (F2.CK to F3.D path delay) = 2.4ns + 9.5ns = 11.9ns Now there is no more setup time violations as follows. Slack2 = Tr2_D Ta2_D = 0.0ns Meet timing requirement. Slack3 = Tr3_D Ta3_D = 0.0ns Meet timing requirement. 2. Problem Description Given (1) a design that has been done cell placement and clock tree synthesis, (2) a static timing report containing all critical paths (maximum delay paths) that are between any two flip-flops, from primary inputs to flip-flops, and from flip-flops to primary outputs, (3) Timing model of clock buffers, the developed software has to apply clock tree optimization techniques such as buffer insertion, gate resizing, and buffer removal, and consider the placement of clock buffers to reduce the number of setup time violation paths and the total negative slack. Basically, one has to take not only setup time problems but also hold time problems into account when applying clock tree optimization to resolve timing violations. Resolving setup time violations may result in new hold time violations, and vice versa. To simply this problem, the contestants need to take care setup time violations only and ignore all hold time violations. 3. Input The default time, capacitance, and distance (coordinate) units are in nano-second (ns), pico-fara (pf), and micron-meter (um), respectively. (1). Design file (design.def) The format of the design file is as follows. DIEAREA (lower-left coordinate) (upper-right coordinate) PINS Pin_name1 Direction X1-coordinate Y1-coordinate Pin_name2 Direction X2-coordinate Y2-coordinate END PINS COMPONENTS Instance_Name1 Cell_Name1 X3-coordinate Y3-coordinate Instance_Name2 Cell_Name1 X4-coordinate Y4-coordinate END COMPONENTS NET 4

5 Net_Name1 Type Instance_Name1.pin1 Instance_Name2.pin1. Net_Name2 Type Instance_Name4.pin2 Instance_Name5.pin2.. END NET lower-left coordinate: the coordinate at the lower-left corner of the die. upper-right coordinate: the coordinate at the upper-right corner of the die Pin_name: the pin name of input, output, and in/out pins Direction: the direction of the corresponding pin. It can be IN, OUT, or INOUT. X-coordinate: the coordinate in X-axis. Y-coordinate: the coordinate in Y-axis. Instance_Name: the instance name of a placed cell. Cell_Name: the cell name of a placed cell. Net_Name: the name of an interconnect. Type: the type of the specified net. It can be CLOCK or SIGNAL. Instance_Name.pin: the pin name of the cell connected to the net. For example, u1/u10/f1.ck represents that the instance name is u1/u10/f1 and CK pin is connected to the net. The slash / stands for hierarchy divider. The sequence of specified instances must be the driving cell first and followed by driven cells. (2). Static timing report file (timing.inf) Note that, in this problem, we only consider setup time constraints. The static timing report file contains the timing information of the critical paths (maximum delay paths) that are between any two flip-flops, from primary inputs to flip-flops, and from flip-flops to primary outputs. The format is defined as follows: #start_point end_point path_delay setup cap s_clk e_clk slack data_in[0] u0/rg_ u1/u10/f1 u1/u10/f u1/u10/f2 u2/f u1/rg_1 u1/u10/f u1/u10/f2 add_out[5] The line begins with # is a comment. start_point: a primary input port or a flip-flop instance name. end_point: a flip-flop instance name or a primary output port. path_delay: the maximum path delay from the start_point clock pin to the end_point data pin. setup: the setup time requirement of the end_point flip-flop. 5

6 cap: the clock pin capacitance of the end_point if the end_point is a flip-flop. s_clk: the clock latency of the start_point clock pin. e_clk: the clock latency of the end_point clock pin. The slack is the required time subtracts the arrival time of the end_point. In the example above, the second (third) row demonstrates the timing information of the path between flip-flops F1 and F2 (F2 and F3) depicted in Fig. 1. The instance names of F1, F2, and F3 are u1/u10/f1, u1/u10/f2, and u2/f3, respectively. data_in[0] is a primary input port and add_out[5] is a preminary output port. (3). Clock buffer s timing model (clkbuf.lib) The given timing model is in Synopsys.lib format and contains timing information and input pin capacitance of clock buffers and inverters only. It is a two-dimension table-look-up model. The timing is related to the input transition time and the output load. Below is an example of the timing model: lu_table_template(delay_template_7x7) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006"); index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006"); cell (CLKBUFX1) { pin(a) { direction : input; capacitance : ; pin(y) { direction : output; capacitance : 0.0; function : "A"; timing() { related_pin : "A"; timing_sense : positive_unate; cell_rise(delay_template_7x7) { index_1 ("0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3"); index_2 (" , 0.021, , 0.084, 0.147, 0.231, "); values ( \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , "); rise_transition(delay_template_7x7) { index_1 ("0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3"); index_2 (" , 0.021, , 0.084, 0.147, 0.231, "); values (\ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , "); Input Capacitance 6

7 cell_fall(delay_template_7x7) { index_1 ("0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3"); index_2 (" , 0.021, , 0.084, 0.147, 0.231, "); values ( \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , "); fall_transition(delay_template_7x7) { index_1 ("0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3"); index_2 (" , 0.021, , 0.084, 0.147, 0.231, "); values ( \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , ", \ " , , , , , , "); The lu_table_template defines the template of the look-up-table. This is a 2-dimension table, where the first index denotes the input net transition time and the second index denotes the total output net capacitance. The output net capacitance includes net load and the input pin load of driven cells. Assume that a CLKBUFX2 buffer drives three CLKBUFX1 and its net load is 10pf. Then, the total output net capacitance is pf (10pf + 3 x pf). Both indexes have 7 elements. The cell_rise and cell_fall groups define cell s rising delay and falling delay of the output pin that related to an input pin. In the example, when input net transition is 0.1ns and the output net capacitance is pf, the cell_rise delay is ns. The rise_transistion and fall_transistion groups define cell s output pin transition time. In the example, when input net transition is 0.1ns and the output net capacitance is pf, the rise_transition time is ns. The output pin transition is used as the input net transition for the delay calculation of next stage. If the input net transition and/or the output net capacitance are not exactly exist in the indexes, the software should use interpolation to calculate the timing. For the details of Synopsys timing model format, please refer to Synopsys Library Compiler Manual. (4). Timing constraint file (timing.con) Timing constraint file specifies the clock cycle time, and the input delay and output delay 7

8 of primary IOs. The format is defined as follows: Clock_cycle clock_name clock_cycle_time Input_delay input_pin_name input_delay_time Output_delay output_pin_name output_delay_time Clock_cycle, Input_delay, and Output_delay are reserved keywords. Input_delay and Output_delay are the external delays of an input pin and an output pin respectively, whose definitions are identical to that defined in Synopsys PrimeTime. As the example shown in Fig. 1 and the example of timing.inf shown in page 5, the timing constraint file is as follows. Clock_cycle CLK 10 Input_delay data_in[0] 4.8 Output_delay add_out[5] Output (1). Design file with optimized clock tree (design_opt.def) The format of the output design file should be identical to that of the input design file. The output design file should contain entire design including optimized clock tree. All placed standard cells except clock buffers cannot be changed or moved. It is not allowed to place clock buffers outside the die area. In other words, the lower-left coordinate and the upper-right coordinate should be the same as those of the input design file. The new placed clock buffers are allowed to overlap the existing placed standard cells. (2). Clock tree timing report (clock.rpt) The format of the clock tree timing report is as below: #start_point end_point s_clk1 e_clk1 slack1 s_clk2 e_clk2 slack2 data_in[0] u0/rg_ u1/u10/f1 u1/u10/f u1/u10/f2 u2/f u1/rg_1 u1/u10/f u1/u10/f2 add_out[5] start_point: a primary input port or a flip-flop instance name. end_point: a flip-flop instance name or a primary output port. 8

9 s_clk1: the original clock latency of the start_point clock pin. e_clk1: the original clock latency of the end_point clock pin. slack1: the original timing slack. s_clk2: the optimized clock latency of the start_point clock pin. e_clk2: the optimized clock latency of the end_point clock pin. slack2: the optimized timing slack. In the example above, the contents of the first two columns are identical to those given in input timing report file (timing.inf), and the following three columns are identical to the last three columns in timing.inf as well. The second (third) row demonstrates the timing information of the path between flip-flops F1 and F2 (F2 and F3) depicted in Fig. 3. (3). Net load file (net_load.rpt) The net load file contains capacitance of all clock nets. The capacitance unit is in pf. # Net_Name capacitance CLK_L0_N CLK_L0_N CLK_L1_N The program doesn t need to perform real routing but it must use the given formula below to estimate the net load for calculating the delay of clock buffers. The formula to estimate the net load C of a driver pin is C = net _ length φ, all _ fanout φ = where the net_length is the net length from driving cell to the driven cell, its unit is in um and its formula is net _ length = X cell1 X cell 2 + Y cell1 Y cell 2 where the (X,Y) is the coordinates of a cell in X-axis and Y-axis, respectively. φ is a capacitance factor and its value is pf/um. 5. Delay Calculation In this problem, we assume the resistance of interconnect is 0 ohm and thus the there is 9

10 no interconnect delay for all nets. The effects of net load, pin capacitance of driven clock buffers, and pin capacitance of flip-flop s clock pin should be taken into account when calculating the cell delay of driving clock buffer. The input capacitances of clock buffers and flip-flops are specified in clock buffer s timing model and timing report file, respectively. Assume that the input transition times of all primary inputs are 0ns and all primary output capacitance are 0pf. 6. Language/Platform Language: C or C++ Platform: SUN OS/Solaris 7. Evaluation The number of setup time violation paths The maximum negative slack of setup time violations. The total negative slack of setup time violations The worst clock latency Run time Memory usage The correctness of net load calculation The maximum negative slack after optimization should be less than or equal to that before optimization. The total negative slack is the summation of all negative setup time slacks. The clock latency should be as less as possible. The final results will be compared with the report from Synopsys PrimeTime, in which the output design (design_opt.def) as well as clock net load (net_load.rpt) will be back-annotated to PrimaryTime to analyze the timing of clock buffers, the clock latencies of all flip-flop s clock pins, and the setup time of all critical paths. Again, all hold time violations can be ignored. 8. Reference [1] J.P. Fishburn, Clock Skew Optimization, IEEE Transaction on Computers, 39(7): , [2] N. Masheshwari and S.S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, second edition, Kluwer Academic Publishers,