IMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR

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1 International Journal of Engineering & Science Research IMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR ABSTRACT Pathik Gandhi* 1, Milan Dalwadi 2, Kinjal Upadhyay 3 1 M.Tech Scholar., VLSI, U.V.Patel college of Engineering and Technology, Ahmedabad, India. 2 M.Tech Scholar, VLSI, U.V.Patel college of Engineering and Technology, Ahmedabad, India. 3 Teaching Associate, einfochips Training And Research Academy, Ahmedabad, India. PLB performance monitor(ppm) is a one of the peripheral of the IBM PowerPC 405 core which is 32-bit RISC CPU for use in custom logic applications The PLB performance monitor (PPM) provides hardware for counting certain events associated with PLB bus transactions. In Synthesis there are three steps: Translation, Optimization, Mapping. In STA (Static Timing Analysis), dividing the circuit into timing path and calculates delay of each timing path with the help of Prime Time tool. The PPC405 core demonstrates the scalability of the PowerPC Architecture in its optimal fit for applications such as Consumer video applications including digital cameras, video games and set-top boxes, handheld GPS receivers, routers, LAN switches, ATM switches, high performance modems, and network interface cards, Industrial machine control and robotics. Keywords: Read, Write, Slack, Setup Time, Hold Time 1. INTRODUCTION The PPM can perform both event-occurrence counting and event-duration counting. Occurrence counting is accomplished via a set of counters that increment their value once for each occurrence of a selected event, until a predefined timer has expired. Duration counting is accomplished via separate registers that increment on every clock cycle that a pre-selected event is active. The PPM consists of a set of counters whose contents may be read by software and used to analyze and enhance PLB performance, or used as a software debug mechanism. Each counter can be individually enabled, and is capable of generating an external interrupt once that counter has reached its maximum value. Event selections and counter controls are performed via the control, status, and individual counter selection registers. 2. SYNTHESIS FLOW Fig 1: Synthesis Flow *Corresponding Author 3023

2 1. Translation: The process which converts RTL level code into gate level design with the help of Design Complier tool. In this step, the cells come from the GTECH Library that is technology independent library. 2. Optimization: In this step first to define technology library and target library[1]. The design is optimized according to different constraints[1] with the help of Synopsys Design Compiler tool. Optimization is done in terms of Timing, Area, and Power. 3. Mapping: Design is mapped with the target technology[1] such as 90 nm, 65 nm. 3. BACKEND SYNTHESIS IMPLEMENTATION OF PROCESSOR LOCAL BUS (PLB) PERFORMANCE MONITOR 3.1 Tools and Technology This design is implemented on 90 nm technology. The tool which is used for backend synthesis is Design Compiler and for Static Timing Analysis (STA) is Prime Time. 3.2 Implementation [Synthesis] First verilog code of this design is read[1] in Design Compiler using read command. This design is optimized according to constraints such as input delay[2], output delay[2], Clock frequency after setting technology library [1], link library [1]. by using compile command. Different techniques are used to optimize timing[3] Timing Results [After giving compile command] of PLB Performance Monitor Compile command executes all constraints and optimizes design in terms of timing, area, power. This timing result is generated by using report_timing[1] command. Slack =Required Time[4] Arrival Time[4] Fig 2: Timing Result [slack violation] If slack is negative value so it means it is violated so it needs to be zero or positive. If slack is 0 or positive then design is working correctly. Copyright 2013 Published by IJESR. All rights reserved 3024

3 This design is again optimized by using compile_ultra [advanced optimization] [1] command Timing Result [After compile_ultra command] Fig 3: Timing Result [slack improved] After giving compile_ultra, for this design slack is improved [figure 3 shows slack is zero] Quality of Report [After compile_ultra command]report_qor[1] Fig 4: Quality Of Report Figure 4 highlights Total Negative Slack is zero., No of Violating paths are zero. It also reports cell count, combinational area, non combinational area. It means this design is working fine Schematic [one of the path in which violation has come] Copyright 2013 Published by IJESR. All rights reserved 3025

4 Fig 5: (After Compile) (After Compile_ultra) After compile the design has different violations. One of the path that is DCM1/max_held_reg[16] has a violation which is shown in figure 5(after compile).technique used to solve this violation is restructuring. In this technique tool rearranges gates according to gates s internal delay in such a manner that overall functionality remains same as shown in Figure 5 (After compile_ultra). With comparison between compile and compile_ultra second input of NAND gate which is connected to a register is different. In compile_ultra second input of NAND gate is a single unit of block means there is no net delay for the same. And tool replaces the gate with small amount of delay. So overall timing would be minimized. In this manner, overall timing is minimized and slack has become zero. After checking these results netlist is generated by using write[1] command Power Result [After compile_ultra command] [report_power][1] 4. STATIC TIMING ANALYSIS Fig 6: Power Report STA is a method of validating the timing performance of a design by checking all possible paths for timing violations. To check violation for each path, Prime Time tool calculates the signal propagation delay along each path. 4.1 Main steps of STA Break the design into sets of timing paths Calculate the delay of each path Check all path delays to see if the given timing constraints are met. Copyright 2013 Published by IJESR. All rights reserved 3026

5 4.2 STA Flow STA Inputs and Outputs For STA, Synopsys Prime Time tool is used. Fig 7: STA Flow Inputs: Netlist (generated in DC tool), Constraints, Libraries Outputs: High Quality Netlist,.sdf (Standard Delay Format)[5],.sdc(Synopsys Design Constraints) 4.3 Implementation Of Static Timing Analysis Of Processor Local Bus (PLB) Performance Monitor After giving all the inputs to Static Timing Analysis Tool, Bottleneck Report has to be generated to check number of violating paths through different cells Bottleneck Report of PLB Performance Monitor Fig 8: Bottleneck Report End Slack Result Copyright 2013 Published by IJESR. All rights reserved 3027

6 Figure 8 shows number of violating paths through different cells and End Slack result shows negative slack values at different paths. Total number of Negative Slack is Solution To Remove Timing Violations For PLB Performance Monitor Figure 8 shows one cell that is U11155 (NAND2X0). To get alternate cell from the Prime Time Tool, get_alternative_lib_cells command is used. After getting alternate cell, that cell is replaced with the appropriate cell. With this technique, cell is replaced with a high driving strength so overall timing would be minimized. get_alternative_lib_cells U11155 [6] swap_cell U11155 saed90nm_typ_ht_pg/nand2x1 [6] Bottleneck Report after swapping U11155 with saed90nm_typ_ht_pg/nand2x1 Fig: 9 Bottleneck Report [after swapping U11155] End Slack Result Figure 9 shows U11135 is replaced with saed90nm_typ_ht_pg/nand2x1which has a higher driving strength. Tool replaces cells with a less internal delay. It shows Bottleneck cost is reduced as before. Total number of Negative Slack is 4. Similarly, all cells which are shown in Bottleneck Report are replaced with different cells which have a higher driving strength. Fig 10: Final Bottleneck Report End Slack Result Copyright 2013 Published by IJESR. All rights reserved 3028

7 Figure 10 shows final Bottleneck Report which has zero Bottleneck Cost. It means there are no violations. End Slack report shows all slack are with positive values Timing Result After Removing All Bottleneck Fig 11: Setup Time Path Type is max then report is for Setup Path Type is min then report is for Hold Figure 11 shows that slack for Setup Time[3]= Required Time[3]-Arrival Time[3] This shows this design is working fine. 5. CONCLUSION =1.91 ns 1.91 ns = 0 ns slack for Hold Time[3]= Arrival Time[3]-Required Time[3] = 0.24 ns Hold Time In this paper we have implemented Backend Synthesis and Static Timing Analysis Of Processor Local Bus (PLB) Performance Monitor by using Synopsys Tools. From this paper, one can have a brief idea of how to do synthesis, Static Timing Analysis of Processor Local Bus (PLB) Performance Monitorby using synopsys tools. REFERENCES [1] Design Compiler User Guide Version F SP2, December 2011 [2] in.html[information about different delays] [Date: 25 th March,2013] [3] different timing optimization techniques] [Date: 2 nd April,2013] Copyright 2013 Published by IJESR. All rights reserved 3029

8 [4] of Static Timing Analysis] [Date: 10 th April,2013] [5] Prime Time Fundamentals User Guide Version F , December 2011 [6] Prime Time Suite Tool Commands Version H , December 2012 [7] [calculation of Setup Time and Hold Time][Date: 14 th April, 2013] [8] [information about constraints file] [Date:5 th April, 2013] [9] PLB Performance Monitor User s Manual[Date: 26 th March, 2013] Copyright 2013 Published by IJESR. All rights reserved 3030

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