EEC 118 Lecture #17: Implementation Strategies, Manufacturability, and Testing
|
|
- Dorthy Horn
- 7 years ago
- Views:
Transcription
1 EEC 118 Lecture #17: Implementation Strategies, Manufacturability, and Testing Stanley Hsu 6/5/2012 Slides courtesy of Rajeevan Amirtharajah and Bevan Baas, UC Davis, Zhiyi Yu, Fudan University, and Jeff Parkhurst, Intel Corp.
2 Permissions to Use Conditions & Acknowledgment Permission is granted to copy and distribute this slide set for educational purposes only, provided that the complete bibliographic citation and following credit line is included: "Copyright 2002 J. Rabaey et al." Permission is granted to alter and distribute this material provided that the following credit line is included: "Adapted from (complete bibliographic citation). Copyright 2002 J. Rabaey et al." This material may not be copied or distributed for commercial purposes without express written permission of the copyright holders. Hsu/Amirtharajah, EEC 118 Spring
3 Announcements Homework 8 due this Friday Last lab this week. Lab 6: 8T SRAM Course evaluations at end of next lecture Final exam: Monday 6/11, 1-3PM in Chem 166. Final review next time Hsu/Amirtharajah, EEC 118 Spring
4 Implementation Strategies Hsu/Amirtharajah, EEC 118 Spring
5 Abstraction of Design Complexity Design complexity Tens of transistors (i.e. logic gate, or analog circuits) Each xtr. hand crafted along with placement and wiring Hundreds of transistors Can be hand crafted (i.e. ALU, register file, filters, and _) Thousands to 100s of thousands of transistors Must find regularity in structure and exploit it (re-use cells) Need CAD tool (i.e. standard cell design, memory) Millions to billions of transistors Must find high-level regularity in structure and exploit it (reuse modules and subsystems) Need CAD tool! i.e. Microprocessor, System on Chip (SOC RF, BB, GPU, MPU, Mem., and etc.), and Hsu/Amirtharajah, EEC 118 Spring
6 Design Abstraction Levels SYSTEM + FUNCTIONAL UNIT, or MODULE GATE CIRCUIT S n+ G DEVICE n+ D Hsu/Amirtharajah, EEC 118 Spring
7 Hierarchical Abstraction Circuit design is really about constructing models While designing at the gate level, we do not consider what is inside each gate, but must select the most appropriate model of the gate. A model of the gate/block is used. Functional/logical Electrical Physical Timing Power Signal Integrity A C A B B C AND AND AND OR OR Carry- Out Hsu/Amirtharajah, EEC 118 Spring
8 Why Learn About Circuits and Layout Then? Best designers can: Construct and apply appropriate model Understand limitations of models multi-disciplinary view required limited attainable performance and energyefficiency Wire or interconnect performance Must update model. i.e. technology scaling Troubleshoot and debug their own designs Hsu/Amirtharajah, EEC 118 Spring
9 Design Aspects that Defy Hierarchy Clock distribution Timing skew Power distribution Sufficient current handling (IR drop) Adequate noise suppression (coupling from clock) Must come up with models to capture these effects. Hsu/Amirtharajah, EEC 118 Spring
10 Design Styles Full Custom Standard Cell Mixed Full Custom and Standard Cell Gate Array Field Programmable Gate Array (FPGA) Examples: Heterogeneous Platforms System On Chip (SOC) AsAP Hsu/Amirtharajah, EEC 118 Spring
11 All transistors and interconnect drawn by hand Full control over sizing and layout Highest area density and higher performance Full Custom Longest time to design maturity [figure from S. Hauck] Hsu/Amirtharajah, EEC 118 Spring
12 Full Custom Design Example Multiplier Chip Hsu/Amirtharajah, EEC 118 Spring
13 Standard Cell Constantheight cells Regular pin locations Cells represent gates, latches, flipflops Placed and routed by software [figure from S. Hauck] Hsu/Amirtharajah, EEC 118 Spring
14 Standard Cell Channels for routing only in older technologies (not necessary with modern processes with many levels of interconnect) [figure from S. Hauck] Hsu/Amirtharajah, EEC 118 Spring
15 Application- Specific Integrated Circuit (ASIC) Hardwired combination of standard cells implements a fixed logic function or FSM (e.g., video codec) Standard Cell Example [Brodersen92] Hsu/Amirtharajah, EEC 118 Spring
16 Combination Standard Cell and Full Custom [figure from S. Hauck] Hsu/Amirtharajah, EEC 118 Spring
17 Soft MacroModules Synopsys DesignCompiler Source: Digital Integrated Circuits, 2nd Hsu/Amirtharajah, EEC 118 Spring
18 Gate Array Polysilicon and diffusion are fixed for all designs Metal layers are customized for particular chips PMOS transistor p-type diffusion polysilicon n-type diffusion NMOS transistor Hsu/Amirtharajah, EEC 118 Spring
19 Unprogrammed Gate Array Isolation Provided by Spacing Hsu/Amirtharajah, EEC 118 Spring
20 Metal connections made to create particular function What logic gate is this? Programmed Gate Array Hsu/Amirtharajah, EEC 118 Spring
21 Gate Array Sea-of-Gates Uncommited Cell polysilicon V DD rows of uncommitted cells GND metal possible contact Committed Cell (4-input NOR) In1 In2 In3 In4 routing channel Hsu/Amirtharajah, EEC 118 Spring 2012 Source: Digital Integrated Circuits, 2nd 21 Out
22 Unprogrammed Sea-of-Gates Array Hsu/Amirtharajah, EEC 118 Spring
23 Programmed Sea-of-Gates Array Isolation Provided by Cutoff Bias Hsu/Amirtharajah, EEC 118 Spring
24 Gate Array Polysilicon and diffusion the same for all designs um example [figure from LETI] Hsu/Amirtharajah, EEC 118 Spring
25 Field Programmable Gate Array (FPGA) Metal layers now programmable with RAM instead of hardwired during manufacture as with a gate array Cells contain general programmable logic and registers [figure from S. Hauck] Hsu/Amirtharajah, EEC 118 Spring
26 Field Programmable Gate Array (FPGA) Chips can now be designed with software User pays for up-front chip design costs All costs: full-custom, standard cell Half: gate array Shared: FPGA User writes code (e.g., Verilog), compiles it, and downloads into the chip Can be used to prototype standard cell (ASIC) design Hsu/Amirtharajah, EEC 118 Spring
27 Heterogeneous Programmable Platforms FPGA Fabric Embedded PowerPC Embedded memories Hardwired multipliers Xilinx Vertex-II Pro High-speed I/O Courtesy Xilinx Hsu/Amirtharajah, EEC 118 Spring
28 Design at a Crossroad: System-on-a-Chip Multi- Spectral Imager 500 k Gates FPGA RAM + 1 Gbit DRAM Preprocessing 64 SIMD Processor Array + SRAM Image Conditioning 100 GOPS Analog µc system +2 Gbit DRAM Recognition Often used in embedded applications where cost, performance, and energy are big issues! DSP and control Mixed-mode Combines programmable and application-specific modules Software plays crucial role Hsu/Amirtharajah, EEC 118 Spring
29 A SoC Example: High Definition TV Chip Courtesy: Philips Hsu/Amirtharajah, EEC 118 Spring
30 Standard Cell Based VLSI Design Flow Front end (logic/rtl design) System specification and architecture HDL coding & behavioral simulation Synthesis & gate level simulation Back end (physical design) Placement and routing DRC, LVS Dynamic simulation and static analysis Hsu/Amirtharajah, EEC 118 Spring
31 Front-End Design Flow Standard Cell Library (from foundary) System Specification (FSM design) RTL Coding (sim.) Synthesis Gate Level (Structural Code) Ex: c =!a & b INV (.in (a),.out (a_inv)); AND (.in1 (a_inv),.in2 (b),. out (c)); Hsu/Amirtharajah, EEC 118 Spring
32 Back-End Design Flow Gate Level (Structural Code) Place & Route Final layout (sent for fabrication) Gate level Verilog DRC LVS Design rule check Layout vs. Schematic check Timing information If timing not met... iterate! Gate level dynamic and/or static timing analysis (STA) Hsu/Amirtharajah, EEC 118 Spring
33 Example: Asynchronous Array of Simple Processors (AsAP) AsAP Project by Prof. Baas VLSI Computation Lab A processing chip containing multiple (6x6) uniform simple processor elements Each processor has its local clock generator and can communicate with its neighbor processors using dual-clock first-in first-out buffers (FIFOs) Source: Hsu/Amirtharajah, EEC 118 Spring
34 Diagram of a 3x3 AsAP More information: Hsu/Amirtharajah, EEC 118 Spring
35 Front-End Design of AsAP MEMORY - Instruction and Data Oscillator FIFO Processor design Communication protocal Tools: HDL Simulators, MATLAB, high-level programming languages, and others. Hsu/Amirtharajah, EEC 118 Spring
36 Back-End Design of AsAP Technology: CMOS 0.18 um Standard cell library: Artisan Tools Placement & Route: Cadence Encounter Final layout edit: icfb (old virtuoso) DRC & LVS: Mentor Graphics Calibre Static timing analysis: Synopsys Primetime Hsu/Amirtharajah, EEC 118 Spring
37 Flow of Placement and Routing 1. Import needed files 2. Floorplan 3. Placement & in-place optimization 4. Clock tree generation 5. Routing 6. Verification Hsu/Amirtharajah, EEC 118 Spring
38 1) Import Needed Files Gate level verilog (.v) Geometry information (.lef) Timing information (.lib) INV (.in (a),.out (a_inv)); AND (.in1 (a_inv),.in2 (b),.out (c)); INV: 1um width AND: 2 um width a INV b AND C INV: 1ns delay; AND: 2 ns delay Delay (a->c): 1ns + 2ns = 3ns Hsu/Amirtharajah, EEC 118 Spring
39 2) Floorplan Size of chip Location of pins Location of main blocks Power supply: deliver enough power for each gate Power Supply (1.8V) Current 1.75V 1.7V VDD (Metal) Gate 1 Gate 2 Gate 3 Gate 4 VSS 1.65V (need another power line) Voltage drop equation: V2 = V1 I * R Hsu/Amirtharajah, EEC 118 Spring
40 2) Single Processor Floorplan Hsu/Amirtharajah, EEC 118 Spring
41 3) Placement and In-Placement Optimization Placement: place the gates on floorplan In-placement optimization Why: timing information difference between synthesis and layout (wire delay) How: change gate size, insert buffers Should not change the circuit function!! Hsu/Amirtharajah, EEC 118 Spring
42 3) Single Processor: Gate Placement Hsu/Amirtharajah, EEC 118 Spring
43 4) Clock Tree Generation Main parameters: skew, delay, transition time Hsu/Amirtharajah, EEC 118 Spring
44 4) Single Processor Clock Tree Hsu/Amirtharajah, EEC 118 Spring
45 5) Routing Connect the gates using wires - Difficult theoretical problem! In practice: Not a click-and-wait process! Steps: Specify routing and timing constraints Connect global signals Connect local signals Issues: Congestion and (clock) coupling Hsu/Amirtharajah, EEC 118 Spring
46 5) Single Processor Layout Area: 0.8mm x 0.8mm Estimated clock frequency: 450 MHz Hsu/Amirtharajah, EEC 118 Spring
47 5) First Generation 6x6 AsAP Layout Area: 30mm 2 36 processors 114 I/O pads Single Processor Hsu/Amirtharajah, EEC 118 Spring
48 6) Verifications After Layout DRC (Design Rule Check) LVS (Layout vs. Schematic) GDS vs. (Verilog + Spectre/Spice module) Gate level Verilog dynamic simulation Mainly check the function Different with synthesis result: clock, OPT Gate level static timing analysis Check all the paths Hsu/Amirtharajah, EEC 118 Spring
49 Useful Design and Simulation Tools Dynamic HDL Simulation Modelsim (Mentor), NC-verilog (Cadence), Active- HDL Dynamic Analog Simulation Spectre (Cadence), Hspice (Synopsys) Synthesis RTL Compiler (Cadence) Design-Compiler, Design-Analyzer (Synopsys) Placement & Routing Encounter & Virtuoso (Cadence) Astro (Synopsys) Hsu/Amirtharajah, EEC 118 Spring
50 Useful Verification Tools DRC & LVS Calibre (Mentor) Diva (Cadence used in EEC 116/119AB) Dracula (Cadence) Static Analysis Primetime (Synsopsys) Hsu/Amirtharajah, EEC 118 Spring
51 Standard cell flow: Design by re-using the same set of logic cells (standard cell library) Many EDA tools to place, route, verify, and automate the design flow Shorter design time Summary Custom flow: - Designed by individual engineers using manual process - Still require EDA tools to help with design verification, rule checks, and simulations. - Time consuming - Requres careful planning! - Closer to target performance Hsu/Amirtharajah, EEC 118 Spring
52 Manufacturability Hsu/Amirtharajah, EEC 118 Spring
53 Design for Manufacturability For class projects or university research, goal is a single working circuit or small number of prototypes Similar scale for industrial research projects Production goal is usually thousands to 100s of millions of working (or at least marketable) parts Must evaluate circuit designs over a range of parameter variations to ensure correct functionality, performance Design for Manufacturability or Statistical Circuit Design encompasses a variety of techniques Yield estimation and maximization, worst-case analysis, etc. Hsu/Amirtharajah, EEC 118 Spring
54 Circuit Parameter Variations All circuit parameters vary some amount due to variations in process, lithography, or environment Geometric parameters: transistor W and L Device parameters: V T, t ox, µ Interconnect parameters: R, C Operating conditions: V DD, T Variations occur both spatially and temporally Circuit-to-circuit on same die (spatial) Die-to-die on same wafer (spatial) Wafer-to-wafer in same fab (temporal) Example: transistor width W = W 0 + W Designer controls Increasing variation Random Hsu/Amirtharajah, EEC 118 Spring
55 CMOS Inverter Example For both NMOS and PMOS: W = W 0 + W L = L 0 + L V T = V T0 + V T k = k 0 + k For capacitor: C load = C 0 + C For entire circuit: T = T 0 + T V DD = V DD0 + V DD Vin Vout C load All these parameters affect circuit performance! Hsu/Amirtharajah, EEC 118 Spring
56 Performance Variation Example Inverter Delay Histogram Q: What kind of simulation is this? Count Propagation Delay (ps) 100 Delay variations with parameters, loading, V DD, and T Hsu/Amirtharajah, EEC 118 Spring
57 Yield Estimation and Maximization Parametric Yield: ratio of total acceptable circuits to total manufactured circuits Design for manufacturability aims to maximize yield (and $$) Yield statistics are usually complicated since circuit performance is complex function of parameters Numerous methods for estimating and maximizing yield Response surface models (RSM): compact analytical model fit to circuit simulations using Design of Experiments Direct Monte Carlo circuit simulations or the RSM can be used to estimate yields Designer controlled parameters then adjusted to maximize yield estimates Hsu/Amirtharajah, EEC 118 Spring
58 Worst-Case Design 1 Given: range of process, voltage, and temperature (PVT) variations Identify: worst (best) cases for performance parameter of interest Corner Analysis: worse case analysis. All max-min combinations of PVT variations. Labeled by NMOS-PMOS pairs, e.g. Typical NMOS-Typical PMOS (TT) Additional corners: Fast NMOS-Fast PMOS (FF), Slow NMOS- Slow PMOS (SS), Fast NMOS-Slow PMOS (FS), Slow NMOS- Fast PMOS (SF) Voltage corners: Nominal V DD +10% and Nominal V DD -10% Can include threshold voltage, too Temperature corners: 0, 27, and 100 o C Hsu/Amirtharajah, EEC 118 Spring
59 Worst-Case Design 2 Identify worst (best) cases for performance parameter of interest Typical Speed Corner (TT) Nominal VDD, room temperature 27 o C, typ. Vth Slow Speed Corner (SS) 0.9 x VDD, maximum temperature 100 o C, max. Vth Fast Speed Corner (FF) 1.1 x VDD, minimum temperature 0 o C, min. Vth Hsu/Amirtharajah, EEC 118 Spring
60 Process Corners Inverter Delay Histogram TT corner Count FF corner SS corner Propagation Delay (ps) 100 Delay variations with parameters, loading, V DD, and T Hsu/Amirtharajah, EEC 118 Spring
61 Summary Design for manufacturability converts a prototype into a real design for large-scale production Statistical models of process, device and interconnect parameters, and operating conditions used to estimate and maximize yield (and profits) Analysis is difficult because of complexity, usually numerical models and many simulations required Variability trend is worsening as processes shrink For example, locations of individual dopant atoms can affect transistor performance Statistical circuit design is becoming as important as performance and power! Hsu/Amirtharajah, EEC 118 Spring
62 Testing Design for test (DFT): constructing designs easy to test. IC testing cost. Automated test pattern generators and checkers As more functionality is packed into a single chip, testing time and complexity increases. Million of chips each need to be tested. i.e. 32 logic inputs -> 2^32=4.2 billion input combinations! Check 1 million combinations in 1 second -> 1.2 hour/chip!! Goal: Maximize testing coverage (minimizes failure probability) in shortest time. Hsu/Amirtharajah, EEC 118 Spring
63 Next Topics: Low power design principles and circuit techniques Future directions in CMOS digital circuits Alternative logic technologies to CMOS Final exam review Hsu/Amirtharajah, EEC 118 Spring
IL2225 Physical Design
IL2225 Physical Design Nasim Farahini farahini@kth.se Outline Physical Implementation Styles ASIC physical design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification
More informationAgenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
More informationECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path
ECE410 Design Project Spring 2008 Design and Characterization of a CMOS 8-bit Microprocessor Data Path Project Summary This project involves the schematic and layout design of an 8-bit microprocessor data
More informationHow To Design A Chip Layout
Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170) Course and contest Intermediate meeting 3 Prof. Dirk Timmermann, Claas Cornelius, Hagen Sämrow, Andreas Tockhorn, Philipp Gorski, Martin
More informationIntroduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
More informationDigital Integrated Circuit (IC) Layout and Design
Digital Integrated Circuit (IC) Layout and Design! EE 134 Winter 05 " Lecture Tu & Thurs. 9:40 11am ENGR2 142 " 2 Lab sections M 2:10pm 5pm ENGR2 128 F 11:10am 2pm ENGR2 128 " NO LAB THIS WEEK " FIRST
More informationAlpha CPU and Clock Design Evolution
Alpha CPU and Clock Design Evolution This lecture uses two papers that discuss the evolution of the Alpha CPU and clocking strategy over three CPU generations Gronowski, Paul E., et.al., High Performance
More informationDigital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
More informationUniversity of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design
University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents
More informationClocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1
ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationSequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
More informationDesign-Kits, Libraries & IPs
Design-Kits, Libraries & IPs Supported CAD tools Design-kits overview Digital, Analog, and RF Libraries IPs Supported CAD tools Design-kits overview ST 65nm Tanner PDK Standard cell Libraries IPs austriamicrosystems
More informationEfficient Interconnect Design with Novel Repeater Insertion for Low Power Applications
Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,
More informationDigital IC Design Flow
Collège Militaire Royal du Canada (Cadence University Alliance Program Member) Department of Electrical and Computer Engineering Départment de Génie Electrique et Informatique RMC Microelectronics Lab
More informationImplementation Details
LEON3-FT Processor System Scan-I/F FT FT Add-on Add-on 2 2 kbyte kbyte I- I- Cache Cache Scan Scan Test Test UART UART 0 0 UART UART 1 1 Serial 0 Serial 1 EJTAG LEON_3FT LEON_3FT Core Core 8 Reg. Windows
More informationLecture 5: Gate Logic Logic Optimization
Lecture 5: Gate Logic Logic Optimization MAH, AEN EE271 Lecture 5 1 Overview Reading McCluskey, Logic Design Principles- or any text in boolean algebra Introduction We could design at the level of irsim
More informationLayout and Cross-section of an inverter. Lecture 5. Layout Design. Electric Handles Objects. Layout & Fabrication. A V i
Layout and Cross-section of an inverter Lecture 5 A Layout Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London V DD Q p A V i V o URL: www.ee.ic.ac.uk/pcheung/
More informationState-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop
Photos placed in horizontal position with even amount of white space between photos and header State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop Michael Holmes Manager, Mixed Signal ASIC/SoC
More informationMeasuring Metastability
Measuring Metastability Sandeep Mandarapu Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Illinois, USA, 62025 ECE595: Masters
More informationTIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING
TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation
More informationINSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043
INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad - 500 043 ELECTRONICS AND COMMUNICATION ENGINEERING Course Title VLSI DESIGN Course Code 57035 Regulation R09 COURSE DESCRIPTION Course Structure
More information7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
More informationCMOS Binary Full Adder
CMOS Binary Full Adder A Survey of Possible Implementations Group : Eren Turgay Aaron Daniels Michael Bacelieri William Berry - - Table of Contents Key Terminology...- - Introduction...- 3 - Design Architectures...-
More informationPower Reduction Techniques in the SoC Clock Network. Clock Power
Power Reduction Techniques in the SoC Network Low Power Design for SoCs ASIC Tutorial SoC.1 Power Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a
More informationEEM870 Embedded System and Experiment Lecture 1: SoC Design Overview
EEM870 Embedded System and Experiment Lecture 1: SoC Design Overview Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw Feb. 2013 Course Overview
More informationVLSI Design Verification and Testing
VLSI Design Verification and Testing Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text Michael L. Bushnell and Vishwani D. Agrawal, Essentials of Electronic Testing, for Digital,
More informationSeeking Opportunities for Hardware Acceleration in Big Data Analytics
Seeking Opportunities for Hardware Acceleration in Big Data Analytics Paul Chow High-Performance Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Toronto Who
More informationDesign Cycle for Microprocessors
Cycle for Microprocessors Raúl Martínez Intel Barcelona Research Center Cursos de Verano 2010 UCLM Intel Corporation, 2010 Agenda Introduction plan Architecture Microarchitecture Logic Silicon ramp Types
More informationLatch Timing Parameters. Flip-flop Timing Parameters. Typical Clock System. Clocking Overhead
Clock - key to synchronous systems Topic 7 Clocking Strategies in VLSI Systems Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Clocks help the design of FSM where
More informationDEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM
DEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM * Monire Norouzi Young Researchers and Elite Club, Shabestar Branch, Islamic Azad University, Shabestar, Iran *Author for Correspondence ABSTRACT
More informationDesign Verification and Test of Digital VLSI Circuits NPTEL Video Course. Module-VII Lecture-I Introduction to Digital VLSI Testing
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-VII Lecture-I Introduction to Digital VLSI Testing VLSI Design, Verification and Test Flow Customer's Requirements Specifications
More informationECE 410: VLSI Design Course Introduction
ECE 410: VLSI Design Course Introduction Professor Andrew Mason Michigan State University Spring 2008 ECE 410, Prof. A. Mason Lecture Notes Page i.1 Age of electronics microcontrollers, DSPs, and other
More informationTesting Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX
White Paper Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX April 2010 Cy Hay Product Manager, Synopsys Introduction The most important trend
More informationCurriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design Department of Electrical and Computer Engineering Overview The VLSI Design program is part of two tracks in the department:
More informationFigure 1 FPGA Growth and Usage Trends
White Paper Avoiding PCB Design Mistakes in FPGA-Based Systems System design using FPGAs is significantly different from the regular ASIC and processor based system design. In this white paper, we will
More informationAims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic
Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go
More informationWhat is a System on a Chip?
What is a System on a Chip? Integration of a complete system, that until recently consisted of multiple ICs, onto a single IC. CPU PCI DSP SRAM ROM MPEG SoC DRAM System Chips Why? Characteristics: Complex
More information路 論 Chapter 15 System-Level Physical Design
Introduction to VLSI Circuits and Systems 路 論 Chapter 15 System-Level Physical Design Dept. of Electronic Engineering National Chin-Yi University of Technology Fall 2007 Outline Clocked Flip-flops CMOS
More information1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.
.Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost $00, get one million miles to the gallon and explode once a year Most of slides
More informationARM Webinar series. ARM Based SoC. Abey Thomas
ARM Webinar series ARM Based SoC Verification Abey Thomas Agenda About ARM and ARM IP ARM based SoC Verification challenges Verification planning and strategy IP Connectivity verification Performance verification
More information數 位 積 體 電 路 Digital Integrated Circuits
IEE5049 - Spring 2012 數 位 積 體 電 路 Digital Integrated Circuits Course Overview Professor Wei Hwang 黃 威 教 授 Department of Electronics Engineering National Chiao Tung University hwang@mail.nctu.edu.tw Wei
More informationINF4420 Introduction
INF4420 Introduction Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Practical information about the course. Context (placing what we will learn in a larger context) Outline of the
More informationEEC 119B Spring 2014 Final Project: System-On-Chip Module
EEC 119B Spring 2014 Final Project: System-On-Chip Module Dept. of Electrical and Computer Engineering University of California, Davis Issued: March 14, 2014 Subject to Revision Final Report Due: June
More informationProgrammable Logic IP Cores in SoC Design: Opportunities and Challenges
Programmable Logic IP Cores in SoC Design: Opportunities and Challenges Steven J.E. Wilton and Resve Saleh Department of Electrical and Computer Engineering University of British Columbia Vancouver, B.C.,
More informationELEC 5260/6260/6266 Embedded Computing Systems
ELEC 5260/6260/6266 Embedded Computing Systems Spring 2016 Victor P. Nelson Text: Computers as Components, 3 rd Edition Prof. Marilyn Wolf (Georgia Tech) Course Topics Embedded system design & modeling
More informationBest Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
More informationImpact of Signal Integrity on System-On-Chip Design Methodologies
EDP 2004 Impact of Signal Integrity on System-On-Chip Methodologies Juan-Antonio Carballo jantonio@us.ibm.com VSIA IMP co-chair Raminderpal Singh IBM Systems and Technology raminder@us.ibm.com VSIA IMP
More informationA Mixed-Signal System-on-Chip Audio Decoder Design for Education
A Mixed-Signal System-on-Chip Audio Decoder Design for Education R. Koenig, A. Thomas, M. Kuehnle, J. Becker, E.Crocoll, M. Siegel @itiv.uni-karlsruhe.de @ims.uni-karlsruhe.de
More informationAsynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton Dept. of Electrical and Computer Engineering University of British Columbia bradq@ece.ubc.ca
More informationTopics of Chapter 5 Sequential Machines. Memory elements. Memory element terminology. Clock terminology
Topics of Chapter 5 Sequential Machines Memory elements Memory elements. Basics of sequential machines. Clocking issues. Two-phase clocking. Testing of combinational (Chapter 4) and sequential (Chapter
More informationNTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
More informationESP-CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation
Datasheet -CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation Overview -CV is an equivalence checker for full custom designs. It enables efficient comparison of a reference design
More informationSystematic Design for a Successive Approximation ADC
Systematic Design for a Successive Approximation ADC Mootaz M. ALLAM M.Sc Cairo University - Egypt Supervisors Prof. Amr Badawi Dr. Mohamed Dessouky 2 Outline Background Principles of Operation System
More informationARM Cortex-A9 MPCore Multicore Processor Hierarchical Implementation with IC Compiler
ARM Cortex-A9 MPCore Multicore Processor Hierarchical Implementation with IC Compiler DAC 2008 Philip Watson Philip Watson Implementation Environment Program Manager ARM Ltd Background - Who Are We? Processor
More informationDigital to Analog Converter. Raghu Tumati
Digital to Analog Converter Raghu Tumati May 11, 2006 Contents 1) Introduction............................... 3 2) DAC types................................... 4 3) DAC Presented.............................
More informationIntroduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems
Harris Introduction to CMOS VLSI Design (E158) Lecture 8: Clocking of VLSI Systems David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH
More informationLecture 7: Clocking of VLSI Systems
Lecture 7: Clocking of VLSI Systems MAH, AEN EE271 Lecture 7 1 Overview Reading Wolf 5.3 Two-Phase Clocking (good description) W&E 5.5.1, 5.5.2, 5.5.3, 5.5.4, 5.5.9, 5.5.10 - Clocking Note: The analysis
More informationAll Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule
All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:
More informationThe MOSFET Transistor
The MOSFET Transistor The basic active component on all silicon chips is the MOSFET Metal Oxide Semiconductor Field Effect Transistor Schematic symbol G Gate S Source D Drain The voltage on the gate controls
More information1. Memory technology & Hierarchy
1. Memory technology & Hierarchy RAM types Advances in Computer Architecture Andy D. Pimentel Memory wall Memory wall = divergence between CPU and RAM speed We can increase bandwidth by introducing concurrency
More informationDesign Compiler Graphical Create a Better Starting Point for Faster Physical Implementation
Datasheet Create a Better Starting Point for Faster Physical Implementation Overview Continuing the trend of delivering innovative synthesis technology, Design Compiler Graphical delivers superior quality
More informationStarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs
White Paper StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs May 2010 Krishnakumar Sundaresan Principal Engineer and CAE Manager, Synopsys Inc Executive Summary IC
More informationSemiconductor Memories
Semiconductor Memories Semiconductor memories array capable of storing large quantities of digital information are essential to all digital systems Maximum realizable data storage capacity of a single
More information«A 32-bit DSP Ultra Low Power accelerator»
«A 32-bit DSP Ultra Low Power accelerator» E. Beigné edith.beigne@cea.fr CEA LETI MINATEC, Grenoble, France www.cea.fr Low power SOC challenges : Energy Efficiency Fine-Grain AVFS solutions FDSOI technology
More informationGETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8
GETTING STARTED WITH PROGRAMMABLE LOGIC DEVICES, THE 16V8 AND 20V8 Robert G. Brown All Rights Reserved August 25, 2000 Alta Engineering 58 Cedar Lane New Hartford, CT 06057-2905 (860) 489-8003 www.alta-engineering.com
More informationDesigning a System-on-Chip (SoC) with an ARM Cortex -M Processor
Designing a System-on-Chip (SoC) with an ARM Cortex -M Processor A Starter Guide Joseph Yiu November 2014 version 1.02 27 Nov 2014 1 - Background Since the ARM Cortex -M0 Processor was released a few years
More informationExample-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm Computer Technology /99 Overview Ultra-Low-Power
More informationObjective. Testing Principle. Types of Testing. Characterization Test. Verification Testing. VLSI Design Verification and Testing.
VLSI Design Verification and Testing Objective VLSI Testing Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut Need to understand Types of tests performed at different stages
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationTesting of Digital System-on- Chip (SoC)
Testing of Digital System-on- Chip (SoC) 1 Outline of the Talk Introduction to system-on-chip (SoC) design Approaches to SoC design SoC test requirements and challenges Core test wrapper P1500 core test
More informationHow To Integrate 3D-Ic With A Multi Layer 3D Chip
3D-IC Integration Developments Cooperation for servicing and MPW runs offering Agenda Introduction Process overview Partnership for MPW runs service 3D-IC Design Platform First MPW run Conclusion 3D-IC
More informationPowerPC Microprocessor Clock Modes
nc. Freescale Semiconductor AN1269 (Freescale Order Number) 1/96 Application Note PowerPC Microprocessor Clock Modes The PowerPC microprocessors offer customers numerous clocking options. An internal phase-lock
More informationModule 7 : I/O PADs Lecture 33 : I/O PADs
Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up
More informationModeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit
Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements
More informationStatic-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology
Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology Nahid Rahman Department of electronics and communication FET-MITS (Deemed university), Lakshmangarh, India B. P. Singh Department
More informationPLL frequency synthesizer
ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 4 Lab 4: PLL frequency synthesizer 1.1 Goal The goals of this lab exercise are: - Verify the behavior of a and of a complete PLL - Find capture
More informationIntroduction to CMOS VLSI Design
Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration
More informationAC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)
AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)
More informationEE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on
More informationDESIGN CHALLENGES OF TECHNOLOGY SCALING
DESIGN CHALLENGES OF TECHNOLOGY SCALING IS PROCESS TECHNOLOGY MEETING THE GOALS PREDICTED BY SCALING THEORY? AN ANALYSIS OF MICROPROCESSOR PERFORMANCE, TRANSISTOR DENSITY, AND POWER TRENDS THROUGH SUCCESSIVE
More informationMcPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures
McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures Sheng Li, Junh Ho Ahn, Richard Strong, Jay B. Brockman, Dean M Tullsen, Norman Jouppi MICRO 2009
More informationArchitectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng
Architectural Level Power Consumption of Network Presenter: YUAN Zheng Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption
More informationRAM & ROM Based Digital Design. ECE 152A Winter 2012
RAM & ROM Based Digital Design ECE 152A Winter 212 Reading Assignment Brown and Vranesic 1 Digital System Design 1.1 Building Block Circuits 1.1.3 Static Random Access Memory (SRAM) 1.1.4 SRAM Blocks in
More informationModule 2. Embedded Processors and Memory. Version 2 EE IIT, Kharagpur 1
Module 2 Embedded Processors and Memory Version 2 EE IIT, Kharagpur 1 Lesson 5 Memory-I Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would Pre-Requisite
More informationArchitectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
More informationAdvanced VLSI Design CMOS Processing Technology
Isolation of transistors, i.e., their source and drains, from other transistors is needed to reduce electrical interactions between them. For technologies
More informationPROGETTO DI SISTEMI ELETTRONICI DIGITALI. Digital Systems Design. Digital Circuits Advanced Topics
PROGETTO DI SISTEMI ELETTRONICI DIGITALI Digital Systems Design Digital Circuits Advanced Topics 1 Sequential circuit and metastability 2 Sequential circuit - FSM A Sequential circuit contains: Storage
More informationLesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
More informationECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly
More informationTiming Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency
Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking
More informationIntroduction to VLSI Programming. TU/e course 2IN30. Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.
Introduction to VLSI Programming TU/e course 2IN30 Prof.dr.ir. Kees van Berkel Dr. Johan Lukkien [Dr.ir. Ad Peeters, Philips Nat.Lab] Introduction to VLSI Programming Goals Create silicon (CMOS) awareness
More informationLow Power AMD Athlon 64 and AMD Opteron Processors
Low Power AMD Athlon 64 and AMD Opteron Processors Hot Chips 2004 Presenter: Marius Evers Block Diagram of AMD Athlon 64 and AMD Opteron Based on AMD s 8 th generation architecture AMD Athlon 64 and AMD
More informationTrue Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique
True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique Priyanka Sharma ME (ECE) Student NITTTR Chandigarh Rajesh Mehra Associate Professor Department of ECE NITTTR Chandigarh
More informationSystem on Chip Design. Michael Nydegger
Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What
More informationClass 18: Memories-DRAMs
Topics: 1. Introduction 2. Advantages and Disadvantages of DRAMs 3. Evolution of DRAMs 4. Evolution of DRAMs 5. Basics of DRAMs 6. Basics of DRAMs 7. Write Operation 8. SA-Normal Operation 9. SA-Read Operation
More informationWhite Paper Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces
White Paper Introduction The DDR3 SDRAM memory architectures support higher bandwidths with bus rates of 600 Mbps to 1.6 Gbps (300 to 800 MHz), 1.5V operation for lower power, and higher densities of 2
More informationContents. Overview... 5-1 Memory Compilers Selection Guide... 5-2
Memory Compilers 5 Contents Overview... 5-1 Memory Compilers Selection Guide... 5-2 CROM Gen... 5-3 DROM Gen... 5-9 SPSRM Gen... 5-15 SPSRM Gen... 5-22 SPRM Gen... 5-31 DPSRM Gen... 5-38 DPSRM Gen... 5-47
More informationDesign and Verification of Nine port Network Router
Design and Verification of Nine port Network Router G. Sri Lakshmi 1, A Ganga Mani 2 1 Assistant Professor, Department of Electronics and Communication Engineering, Pragathi Engineering College, Andhra
More informationVARIATION-AWARE CUSTOM IC DESIGN REPORT 2011
VARIATION-AWARE CUSTOM IC DESIGN REPORT 2011 Amit Gupta President and CEO, Solido Design Automation Abstract This report covers the results of an independent worldwide custom IC design survey. The survey
More information