Semiconductor Memories

Transcription

1 Semiconductor Memories Semiconductor memories array capable of storing large quantities of digital information are essential to all digital systems Maximum realizable data storage capacity of a single chip doubles every two years On-chip memory have become a widely used subsystem in many VLSI circuit Prof. Gaetano Palumbo 1 Semiconductor memory read-write RWM read-only ROM nonvolatile read-write NRWM non random access random access EPROM E PROM FLASH FIFO, LIFO CAM static SRAM dynamic DRAM Prof. Gaetano Palumbo 1

2 Memory characteristic Capability to store data, Memory Size (bit, byte or word) Time needed to retrieve data, read-access (delay between the read request and the time the data is available) Time elapsed between a write request and the final writing of data, write-access Minimum time required between successive reads or writes, cycle time (it is greater than the access times. It can be different for write or read operation, but it is assumed equal for simplicity) Prof. Gaetano Palumbo 3 Read cycle READ Read access Read access Write cycle WRITE Data Valid Write access DATA Data written Prof. Gaetano Palumbo 4

3 Memory architectures S0 S1 S S n- S n-1 Word 0 Word 1 Word Word n- Word n-1 Storage cell (bit) Input-Output A0 A1 A k-1 d ec o d er k = log n S0 S n-1 Word 0 Word 1 Word Word n- Word n-1 Input-Output A decoder is inserted to reduce the number of select signals (A o A K-1 address word) Prof. Gaetano Palumbo 5 In order to optimize the area of the memory the shape of the core should be almost square A k A k+1 A m-1 Word line d e r c o o w d e r A o A k-1 Input-Output Word 0 Word 1 Word Word N- Word N-1 sense amplifiers column decoder storage cell (word) bit line Prof. Gaetano Palumbo 6 3

4 It is common to reduce voltage swing of bit line to reduce propagation delay, power consumption, cross talk interfacing with external word is achieved via sense amplifiers which give full rail-to-rail swing The architecture works well up to range of 64 Kbits to 56 Kbits (larger memories suffer of speed degradation due to excessively long bit and word lines) Prof. Gaetano Palumbo 7 Higher memories are partitioned into P smaller block (it is added the block address) the local word and bit lines are reduced non active block can be powered off Block 0 Block j Block p-1 row address column address block address Control circuitry block selector Global amplifier/driver input/output Global data bus Prof. Gaetano Palumbo 8 4

5 I/O interface has an enormous impact on the global memory performance (control and timing) DRAM use multiplexed addressing scheme (the lower and upper halves of the address are presented sequentially) reduced number of package pins it is needed strobe signals for each part of the address SRAM uses a self-timed approach (the complete address is presented at once) Prof. Gaetano Palumbo 9 Read-Only Memories NOR ROM WL 0 WL 1 GND WL WL 3 GND Prof. Gaetano Palumbo 10 5

6 A bit has a 0 value if the a MOS is present Each column woks has a pseudo-nmos NOR the design follows the same guidelines of the ratioed logic (pseudo-nmos) V OL equal to 1 to 3 volt for a 5 V power supply The array is constructed by repeating the same cell (in both the horizontal and vertical directions), mirroring the odd cells around the horizontal axis to share the ground line Prof. Gaetano Palumbo 11 The memory is programmed by a selective addition of metal-to-diffusion contact. (the presence of a contact means a 0-bit) WL 0 WL 1 Basic cell 10λ x 7λ WL WL 3 Metal 1 over diffusion GND (diffusion) Prof. Gaetano Palumbo 1 6

7 A denser solution uses an extra implant step to be able to set the MOS threshold to a voltage higher than the power supply (in that case transistor is off) Threshold rising implant WL 0 Basic cell 8.5λ x 7λ WL 1 WL Metal 1 over diffusion GND (diffusion) WL Prof. Gaetano Palumbo 13 A denser solution is NAND ROM since does not requires ground lines A transistor represent a 1 bit value NAND ROM WL 0 WL 1 WL WL 3 The word line operates in reverse logic mode (all word line are high for default) Prof. Gaetano Palumbo 14 7

8 The core area can be almost two times lower than other solutions Basic cell 5λ x 6λ WL 0 WL 1 WL Threshold lowering implant WL Worst performance since a wider pull-up load is needed (higher parasitic capacitances) Prof. Gaetano Palumbo 15 To reduce ROM power dissipation a precharged approach can be adopted Vpre WL 0 WL 1 GND WL WL 3 GND Prof. Gaetano Palumbo 16 8

9 Nonvolatile Read-Write Memories The architecture of the NVRW memories is virtually identical to the ROM structure They make use of transistor threshold which can be electrically altered To reprogram the memory, it need before to be erased The erasing methods differs for the various classes of NVRW The programming takes typically more time of the reading time (an order of magnitude) Prof. Gaetano Palumbo 17 Floating Gate Transistor The core of every NVRW is made by a floatinggate transistor Floating-gate transistor has the threshold voltage programmable Floating gate Source Gate Drain tox t ox n+ p n+ Prof. Gaetano Palumbo 18 9

10 To program the memory an high voltage in the range 15-0 V between source and gate-drain must be used When the programmable voltage is applied the high electric field causes avalanche injection (Electrons acquire sufficient energy to become hot and traverse the first oxide insulation) The phenomenon can occur with oxide as thick as 100 nm (simply to realize) and is self-limiting For the programming mechanism it is also called FAMOS (Floating-gate Avalanche-injection MOS) Prof. Gaetano Palumbo V 5 V 0 V 0 V n+ p n+ Avalanche injection the floating gate change its voltage which is ideally half of the gate 0 V -5 V 0 V n+ p n+ 5 V -.5 V 5 V n+ p n+ Removing programming voltages leaves charge trapped It is equivalent to a voltage offset Although the gate is at the power supply, the floating gate voltages is much lower than threshold voltage Prof. Gaetano Palumbo 0 10

11 EPROM Erasable-Programmable Read-Only Memory is erasable using ultraviolet light via a transparent window in the package are simple and dense erasure is slow (from seconds to minutes) programming takes several (5-10) µs/word erase/program cycle is limited to one thousand Prof. Gaetano Palumbo 1 EEPROM (E PROM) Electrically-Erasable Programmable Read-Only Memory provides electrical-erasure procedure are based on a modified floating gate transistor called FLOTOX (floating-gate tunneling oxide), which uses the Fowler-Nordheim tunneling effect The effect arises using dielectric thickness lower than 10 nm Source Drain n+ p n+ Prof. Gaetano Palumbo 11

12 The main advantage of the effect is that it is reversible The bidirectionality of the effect poses the problem of threshold control (removing too much charge can determine a depletion device always on), and to remedy to it a transistor in series is introduced (it acts as access device) WL Prof. Gaetano Palumbo 3 EEPROM are larger than EPROM (two transistors in each cell and FLOTOX is larger than FAMOS due to extra area for tunneling oxide) Fabrication of very thin oxide is a challenging and costly manufacturing step Advantages are their versatility Can support up to 10 5 erase/write cycle Programming can take from almost 10 ms/word (few s/chip) Prof. Gaetano Palumbo 4 1

13 FLASH FLASH Electrically-Erasable Programmable Read-Only Memory Combines EPROM density with E PROM versatility Uses avalanche hot-electrons-injection to program the device and the Fowler-Nordheim tunneling to erase it Erasure is performed in bulk for a complete core or for a subsection. This reduce flexibility, but allows to avoid access transistor (the threshold can be electronically controlled during erasure) Unlike E PROM erasure occurs with gate grounded and applying and high voltage (1 V) to the source Prof. Gaetano Palumbo 5 SRAM 6T cell WL M M4 M5 Q M1 Q M6 M3 Access is enabled by M5 and M6 Two bit line are used (although they are not necessary, this improves noise margin during read and write operations) Prof. Gaetano Palumbo 6 13

14 6T write operation WL=V DD M 0 M4 Q=0 M5 1 M1 =1 Q=1 0 M6 M3 =0 M4, M6 is a pseudo NMOS and to toggle the memory must be its V OL < / M5 is diode connected and to toggle its source should be > / (M1 is in triode region) Prof. Gaetano Palumbo 7 β [ ( V V ) V ] V = ( V V ) p 4 DD tp OL OL β n 6 [ DD t V OL ] V OL W µ p W L 6 µ n L 4 β 5 1 VDD VDD βn VDD n V V Vt 5 ( DD to ) = W L 5 3 VDD V VDD V to t5 V DD W L Prof. Gaetano Palumbo

15 6T write operation WL=V DD M 0 M4 = C bit M5 Q=0 Q=1 M6 M1 M3 =V C bit DD The bit line are precharged to To do not destroy information we have to guarantee that the source of the diode connected M5 stay lower than / (M1 is in triode region) Prof. Gaetano Palumbo 9 β ( ) 5 1 V DD VDD β = n VDD n VDD Vto Vt 5 W L 3 V DD V ( VDD / Vt 5 ) 1 5 to V DD W L This condition is opposite to that found for writing operation, but it is stronger (to write the memory we can only satisfy the first condition) W / L 1 W / L W / L W / L W / L = W / L ( ) = ( ) = ( ) 3 = ( ) 4 = ( ) 5 ( )6 Prof. Gaetano Palumbo 30 15

16 The second bit line clamp to making extremely difficult to toggle the cell during the read operation (advantage of the dual bit-line architecture) To further prevent the toggling during the read operation the bitline are precharged / (makes impossible to reach the threshold voltage of the inverter) The transient behavior is limited by the read operation since the large bit-line capacitance must be discharged The write time is dominated by the propagation delay of the cross-coupled inverter pair Prof. Gaetano Palumbo 31 The 6T cell while simple and reliable it is areahungry (its dimension are dominated by wiring and interlayer contacts) M M4 Q Q M1 M3 M5 M6 GND WL Prof. Gaetano Palumbo 3 16

17 4T cell WL R R Q M3 M1 Q M4 M 4T cell is 1/3 lower than the 6T cell a very high and compact resistance is used which is implemented with undoped polysilicon (sheet resistance TΩ/ ) Prof. Gaetano Palumbo 33 DRAM To reduce RAM dimension we can eliminate the load which has the only function to replenish the charge lost by leakage RAM cells need a periodical refresh, which typical occurs every 1 to 4 ms Common DRAM are based on the 3T and 1T cells In DRAM the information is represented by charge stored on capacitor In contrast to SRAM, no constraint exist on the device ratio Prof. Gaetano Palumbo 34 17

18 3T cell WWL 1 RWL M1 X C s M3 M The cell is written placing the appropriate data value on 1 and asserting WWL (write word line) To read the cell the RWL (read word line) is asserted and the data is on which is precharged (or clamped to a voltage via a load) Prof. Gaetano Palumbo 35 Write and read cycle WWL 1 RWL M1 X C s M3 M WWL RWL X 1 VDD -VT -VT V Prof. Gaetano Palumbo 36 18

19 1 GND RWL M3 M WWL M1 The cell complexity is substantially reduced compared to the SRAM (576 λ compared to 109 λ ) Prof. Gaetano Palumbo 37 1T cell WL X C s C The cell is written and red asserting WL is precharged to / Prof. Gaetano Palumbo 38 19

20 Write and read cycle WL X V C = S CS + C ( V V ) PRE C C s charge transfer ratio (1% -10%) Write 1 Read 1 WL X V / DD -VT V / / sensing Prof. Gaetano Palumbo 39 C S is typically one or two order of magnitude lower than C Bl ( V around 50 mv). 1T DRAM requires sense amplifier for each bit line (in the other memory it is introduce to speed up the read-out) Unlike 3T, read-out of the 1T DRAM cell is destructive (after a successful read operation the value must be restored) The 1T cell requires the presence of extra capacitance (its minimum value is around 30 ff) To avoid the threshold voltage lost when writing a 1, bootstrapping can be used Prof. Gaetano Palumbo 40 0

21 1T DRAM using a polysilicon-diffusion capacitance n + n + Inversion layer (induced by plate bias) Cross section Layout Prof. Gaetano Palumbo 41 1