Design-Kits, Libraries & IPs
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1 Design-Kits, Libraries & IPs
2 Supported CAD tools Design-kits overview Digital, Analog, and RF Libraries IPs Supported CAD tools Design-kits overview ST 65nm Tanner PDK Standard cell Libraries IPs
3 austriamicrosystems 0.35µm CMOS 0.35µm SiGe 0.35µm HV-CMOS 0.18µm CMOS 0.18µm HV-CMOS
4 austriamicrosystems Supported CAD Tools Schematic & Design Entry Electrical Simulation Digital Simulation Logic Synthesis Layout & Verification P&R Cadence Composer (CDS) Spectre (CDS) Hspice Ultrasim NC-Sim, AMS-Designer Verilog BuildGates Virtuoso-XL Diva Assura SOC Encounter Silicon Ensemble Mentor Synopsys DA (MGC) Eldo (MGC) ModelSim Leonardo IC / Calibre IC-Route Design Compiler Hspice VSS / VCS Design Compiler StarRCXT Astro / ICC Tanner SimulationModels S-Edit TSpice TSpice --- L-Edit DRC Pspice (CDS) Saber (Synopsys) ADS (Agilent) Smash (Dolphin) SmartSpice (Silvaco) SPR
5 AMS Design-Kits Current distributions : Cadence (SUN / Linux) Mentor (SUN / Linux) Tanner (MS-Windows) CDB OA - - C35 (0.35µm CMOS) S35 (0.35µm SiGe) H35 (0.35µm HV-CMOS) C18 (0.18µm CMOS) H18 (0.18µm HV-CMOS)
6 AMS Libraries LV Digital standard cells and IO Libraries : CORELIB : General purpose digital library CORELIB_3B : Same as CORELIB with 3 busses (VDD, VSS, GND) IOLIB : IO pads (input, output, bidir). 3.3V and 5V available IOLIBC_3B : Core limited digital IO Libraries Core and IO cells are characterized for 1.8V, 2.2V, 2.7V, 3.3V. HV Digital standard cells and IO Libraries : CORELIB_HV : CORELIB for high voltage. IOLIB_HV : High Voltage digital IO pads library Analog standard cells Libraries : IOLIB_ANA : Analog IO pads library IOLIBC_ANA_3B : Core limited Analog IO pads library IOLIB_ANA_HV : High Voltage Analog IO pads library A_CELLS : Analog Library RF standard IO cells Libraries : SPIRAL : Library with characterized Inductors RF_PADS : RF IO pads library
7 AMS IP Blocks IP blocks available from CMP free of charge to Univ. & Research (0.35µ CMOS) Single & Dual Port RAMS configurations: Single Port RAM Dual Port RAM Diffusion ROM Bits Words SP SP SP SP SP 256 DP SP / DP SP 512 SP SP 600 SP 1024 SP / DP SP / DP 2048 SP SP / DP SP 4098 DP
8 STMicroelectronics HCMOS9 (130nm CMOS) HCMOS9-SOI (130nm CMOS-SOI) BiCMOS9-MW (130nm CMOS) CMOS065 (65nm CMOS) CMOS065-SOI (65nm CMOS-SOI) CMOS040 (40nm CMOS) CMOS028 (28nm CMOS) New 28FDSOI (28nm FD-SOI)
9 STMicroelectronics supported CAD Tools IC Electrical Simulation Verification Parasitics Extraction P&R CDB OA Spectre (CDS) Eldo (MGC) Hspice (SNPS) ADS (Agilent) Calibre (MGC) StarRCXT (SNPS) Calibre (MGC) QRC (CDS) Encounter (CDS) ICC (SNPS) HCMOS9 x x x x x x x x HCMOS9- SOI x x x x x x x - - BiCMOS9- MW x x x x x x x x x CMOS065 x x x x x x x x x x x CMOS065- SOI x x x x x x CMOS040 x x x x x x CMOS028 x x x x x x x CMOS028 x Q x x Q x x Q x x
10 STMicroelectronics Design-Kits Current distributions : Cadence (SUN/ HP / Linux) HCMOS9 9.2 HCMOS9-SOI 10.0 BICMOS9-MW 2.4a Tanner (MS-Windows) CMOS / V3 CMOS065-SOI 4.2 CMOS / 2.3 CMOS FDSOI 2.0a RF option available for HCMOS9 & CMOS065 design kits.
11 ST 65nm Tanner PDK Full-Custom design environment (Frontend + Backend) All basic devices have been ported from the ST environment to the Tanner Tools. Frontend : - Schematic Capture using S-Edit. - Spice simulation using TSpice. Backend : - Layout Edition using L-Edit. - Parametic layout cells (T-Cells) - Verification using L-Edit/DRC and LVS. New To be done : - Standard-cells (schematics and abstracts) - Qualifying the HiPer Design Suite
12 Standard Cells Libraries from STMicroelectronics CORE cells Libraries : CORE : General purpose core libraries CORX : Complementary core libraries (complex gates) CLOCK : Buffer cells and the same for clock tree synthesis PR : Place and route filler cells and the same. DP : Datapath leaf cells libraries HD : High density core libraries IO cells Libraries : 1.8V, 2.5V, 3.3V IO pads: 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog Staggered IO pads Flip-Chip pads Level Shifters, and compensation cells On request: LVDS Pads DLL, PLL Memories SPRAM / DPRAM / ROM available on request, free of charge (1-2 weeks delay) on request
13 IP Blocks Available from STMicroelectronics ARM 946EJ-S : HCMOS9 130nm CMOS IP core Simulation models Abstract view for P&R Timing Files for STA and backannotated simulation Available under NDA ARM 926EJ-S : CMOS065 65nm CMOS IP core Simulation models Abstract view for P&R Timing Files for STA and backannotated simulation Available under NDA + Access to all available ARM cores in 65nm.
14 Design-Kit Support at CMP Management and support of the DK distribution and updates. Development, support and maintenance of design-kits. Tutorials on some design flows. Two CMP engineers working partly at ST to solve all kind of support with ST design-kits and memory blocks generation.
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