PLL frequency synthesizer

Transcription

1 ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 4 Lab 4: PLL frequency synthesizer 1.1 Goal The goals of this lab exercise are: - Verify the behavior of a and of a complete PLL - Find capture range and lock range of a PLL - Verify the operation of various frequency synthesizers based on PLLs 1.3 Required instruments and devices Power supply 5 V (Vdd), signal generator (1 MHz, CMOS compatible), scope, frequency meter, multimeter. The circuit operation must be verified with the scope; if available, use frequency meter for frequency measurements, and DVM for voltage measurements. The PLL is based on the CD 4046 integrated circuit; the synthesizer uses programmable 4-bit counters (CD 4029). The data sheet of both circuits can be found in the manufacturer websites and in the course website (Learning materials Data sheet). Passive devices: R and C for the and the loop filter, pull-up Resistors and switches for counter commands (or board with wired switches, pullup resistors, and LEDs). 1.4 Design specifications Design the to operate in the 100 khz 500 khz range. The loop filter should be designed for a capture range khz (about ½ the lock-in range) when using Phase Detector () I, and for cutoff frequency 10 khz (1/10 of minimum input frequency) when using II. 1.5 Most common problems and mistakes Remember that in CMOS circuits inputs cannot be left floating. Every input pin must receive a voltage corresponding to a correct logic state (obviously, outputs should not be short-circuited to GND or Vdd). When setting the signal generator output level, remember that no IC pin can accept a voltage outside the supply range (GND Vdd for single-supply circuits). That means the maximum allowed input voltage range is 0 5V. AC coupling at PLL Vi input is acceptable. The filter and the external resistors must have rather high values; too low values cause high current at the CMOS outputs. Page 1 of 5

2 2. - Measurements 2.1 f(vc) characteristic The task is to plot the characteristic (open loop), to verify the frequency range where the PLL can operate. - wire the open-loop circuit (no connection between the loop filter and the ); - apply to the control input an external voltage Vc, ranging from GND to Vdd (use a potentiometer connected between GND and the supply voltage Vdd), - change Vc and measure the frequency fo, - Plot fo(vc), - Evaluate the gain Ko (Hz/V). This measurement allows to verify the actual frequency range of the, and the consequent expected operating range of the synthesizer. The IC has wide tolerances on analog parameters, which may cause a significant difference between expected and measured values Lock-in and capture range r this measurement and the following ones, the lock can be verified on a scope from Vi and Vo signals. When the loop is locked, the signals have the same frequency and constant phase difference, and look steady on the screen. When unlocked, phase changes continuously, and only the channel used to synchronize the scope looks steady (the other one looks like a signal not synchronized). Sometimes signals look steady, but frequencies are different; in this case the PLL is on harmonic lock (M = NFi). To check actual lock, make small changes in external reference generator frequency (), and verify consequential changes in the signal (Fu). - the 4046 includes a bias network to set the correct DC of the input signal (to cross the first buffer threshold), therefore the Vi signal must be applied through a capacitor. The high-pass cell should pass the lowest frequency of the input signal Vi with little attenuation. To compute the C value, assume Zi = 500 k for the 4046 signal input. - Apply to the input a sine or a squarewave signal, with Vpp = Vdd/ Lock-in and capture range with I I (XOR circuit) allows to get different capture and lock-in ranges. The loop filter cutoff frequency used for II would give a very narrow capture range, therefore it is necessary to design and use a new filter as described in the 4046 data sheet. - Change filter components and move loop filter input to I output, - Measure capture and lock-in ranges (use slow changes of input signal frequency), - Verify the phase error change as the input signal frequency moves through the lock range. I will be no longer used for the following experiments. Moreover, an actual measurement of phase error require some time. If the goal is only to verify the synthesizer operation, the last point of this experiment can be postponed or skipped. Page 2 of 5

3 2.2.2 Lock-in and capture range with II This measurement aims to find the lock-in and capture ranges for II (charge pump PFD). - Insert a loop filter with cutoff frequency about 1/10 of the minimum frequency. - Close the loop using II (sequential circuit). - Change input frequency on a range slightly wider than the range measured in step 2.1, and find capture and lock-in ranges. II is a charge pump circuit, and brings an infinite equivalent DC loop gain. With slow changes in the input frequency (such as hand-made frequency changes in the Vi external signal generator), capture range and lock-in range are the same, and phase error is always zero. This test requires very slow changes in the input frequency, and accurate frequency measurements (use the frequency meter). 2.3 equency multiplier (2 M ) r this measurement and the following ones use II, with Ra-Rb-C loop filter (pole-zero network), with Ra*C = 10/Fimin, and Rb = Ra/100. The first step is the setup of a constant-ratio frequency multiplier. Ra Rb C - Prepare a modulus-4 frequency divider using the programmable counter CD4029, and verify the circuit operation (set the CD 4029 for continuous x 16 counting, use the second FF output). - Insert in the loop, between the output and input, the modulus-4 divider. - Apply at input a 80 khz signal. - Verify PLL operation (with small changes of ), and the output frequency. The multiply coefficient (divider ratio) can be changed in power of 2 (2, 4, 8, 16), just by shifting the output to other stages of the counter. Verify operation for different counter ratios; for each setting select a reference frequency so that the output frequency (Fu) lies within the range. Verify that changing the reference frequency, the frequency Fu changes according to the multiply ratio. : Fu Fi To select the loop filter pole position consider that here the and the filter F operate at a frequency Fi = = Fu/N (different from frequency). The cutoff frequency must be scaled by the same factor N from the previous experiment (loop without divider). To move pole and zero position keeping the same ratio, change only the filter capacitor. The experiments and measurements in the following are optional; prepare the design, but carry out the experiment only if there is enough time after the previous ones. Page 3 of 5

4 2.4 Variable frequency synthesizer (multiply by N) This section describes a simple variable module frequency synthesizer. It requires a variablemodulus counter, which can be build using the CD 4029 (or other integrated counters). With any logic CMOS IC, to apply 0/1 at programming inputs use a pull-up resistor and a switch (or a wire) to GND. With open switch (or open wire) the pullup brings the input to a High state (1); when the switch (or wire) is closed to GND the logic state is Low (0). A module with pull-up and switch array is available in the LED lab. To get variable ratios, the counter must be preset through the jam inputs to a suitable value, reloaded when Terminal Count state (16) is reached. E.g., loading 11 (decimal) with cause the counter to loop through the sequence 11, 12, 13, 14, 15, 16=11 (five states). To use directly TC as Load command, add an inverter. It is also possible to use Q4 as Load command, but only the first 3 FFs can be used for programming (Q4 must be preset to 0). - Prepare a circuit with the CD4029 counter, wired to change the counter ratio N in the range from 2 to 7 (or 2-15). - Verify the counter operation placing the counter outside the PLL loop (use at fixed frequency as clock). Change counter ratio. - Insert the programmable counter in the loop, between the output and input. - Verify correct operation of the PLL over the complete range of N. - Measure the frequency of the for different counter coefficients N (at least 4 cases). : N JA M IN F1 F2 Here too the reference frequency must be properly selected. r instance, for lock range khz and 2 to 7 division, = 60 khz. 2.5 Integer synthesizer (M/N) This section describes some measurements on an integer synthesizer (M/N). - Insert a binary counter (divide by M = 2 P ) on the reference signal (equency = 1 MHz). - Insert the divide by N counter between and. - Verify the Vi signal and the output Vo for P = 1, 2, 3, 4, with N = 2. - Verify the Vi signal and the output Vo for P = 1, 2, 3, 4, with N = 16. Does the PLL keep lock for all P values? - Verify the Vi signal and the output Vo for P = 1, 2, 3, 4, with N variable in the range 2 to 15. Verify for which (P, N) pairs the PLL stays locked. - Change the reference signal counter in a modulus M frequency divider. Use the same circuit as in Verify combinations of extreme values for M and N, and some intermediate cases. r M and N in the range 1 to 16, definer the relation to answer the following questions: - If = 100 khz, which is the total frequency range of the synthesizer? - Which is the minimum synthesizer step (channel spacing)? Describe how the circuit ( and filter) should be modified to get operation over any M, N combination (with = 100 khz). Page 4 of 5

5 2.6 actional synthesizer This section describes some measurements on a fractional synthesizer. - Connect Fi to ; - Insert a modulus K divider on F2 signal. Use the MSB of the counter to change the coefficient of the divider (change the LSB of the divider). - Measure the frequency (with PLL locked), and verify the / ratio. Fk : K : M or N F1 F2 - Design and build a combinational circuit to decode states of the modulus K counter, and use the output to switch N/(N+1). This circuit allows to change the duty cycle of the N/(N+1) switching. - Verify circuit operation, and measure frequency and the ratio with. 3 - Lab report The design results are only the values of passive and loop filter components. Provide these data for each circuit configuration. Draw detailed schematic for each configuration, with the following rules: - use functional symbols - IC pin labels (related with pin function) should be inside the symbol - IC pin number written outside the symbol - no topographic diagram (a photo of the circuit may be acceptable) Draw timing diagrams, with relevant information (e.g. signal frequency). Discuss the limits of each configuration, and the disagreements between expected results and actual behavior. Page 5 of 5