Impact of Signal Integrity on System-On-Chip Design Methodologies
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1 EDP 2004 Impact of Signal Integrity on System-On-Chip Methodologies Juan-Antonio Carballo VSIA IMP co-chair Raminderpal Singh IBM Systems and Technology VSIA IMP co-chair April IBM Corporation
2 Juan-Antonio Carballo EDP 2004 Introduction! Signal integrity First-order concern in System-on-a-Chip (SoC) design! SoC methodologies need to be fundamentally transformed Must develop techniques to enhance block reuse while accounting for signal integrity! Reuse standards work can help achieve this goal Virtual Socket Interface Alliance (VSIA) " focus on reuse Signal Integrity (SI) sub-working group " focus on SI in SoC Work integrates with SoC methodologies and enhances block reuse
3 Juan-Antonio Carballo EDP 2004 Example " Power Grid Issues Package Grid Current + V DD Decoupling Capacitance Load time! With package, maximum noise becomes: V max l µ t p R g + µl µ R 2 g C d (1 e -t p/τ ) DC Package Decap
4 Juan-Antonio Carballo EDP 2004 Example " Power Grid Issues Semi-custom Voltage Islands! Reduce power, low overhead, better supply But other IP integration issues V dde V dde Receiver Medium data Analog Receiver Sampler and critical logic Voltage regulator (shareable) Scannable shifters V ddi Clock generation Semi-custom Clock and Data Recovery Recovered data
5 Juan-Antonio Carballo EDP 2004 Example " Power Grid Issues Reduced Impact of Supply Variation! Effective supply variation reduced But need to account for regulator-logic / inter-island interaction Effective supply Impact (V) Nonregulated Regulated
6 Juan-Antonio Carballo EDP 2004 Example " Power Grid Issues: Test Chip PLL Vref & Regulator High power logic Low power logic
7 Juan-Antonio Carballo EDP 2004 VSIA Signal Integrity Sub-DWG! Part of Implementation DWG Implementation-verification, AMS, SI! Scope Digital and analog blocks Signal integrity issues Power grids, X-talk, substrate coupling, electromigration! Goals Facilitate exchange of digital & analog blocks in SoCs Improve author-integrator communication of SI issues! Assumptions The blocks are provided for integration as hard blocks
8 Juan-Antonio Carballo EDP 2004 Focus! Interconnect crosstalk! Signal Electromigration! Supply and ground grid noise and electromigration! Substrate coupling
9 Juan-Antonio Carballo EDP 2004 Format! Deliverables Include detailed tables Aid with implementation! Guidelines Textual advice
10 Juan-Antonio Carballo EDP 2004 Example Table Entry! Interconnect Crosstalk (Voltage Noise and Delay Variance) Electrical data Number Description Maximum permissible noise propagating into input ports Format VC Hspice Mandatory? Conditionally Comments If available, otherwise document in Section 2.4
11 Juan-Antonio Carballo EDP 2004 Team! Main participants (not TSMC) Motorola IBM Simplex Intel Startups (e.g. CommLSI) Japan
12 Juan-Antonio Carballo EDP 2004 Interconnect Crosstalk (Voltage Noise and Delay Variance) Electrical data Maximum noise at ports Max crosstalk for sensitive nets Physical data Location of sensitive polygons Electrical characteristics for aggressors and sensitive nets Location of strong potential aggressors or No-fly zones Best, worst case slews at ports Max load/rc at ports Location of top-layer/peripheral supply wires Safe regions for OTH signals (possibly classified by slew)
13 Juan-Antonio Carballo EDP 2004 Signal Electromigration Logical data Mutex/One-hot relationships required between signals Physical data Layout Electrical data Current density limits,metal/via Max load on ports Max slew rate on inputs Max Switching factor Drive Strength Timing data Variation of timing arcs within VC with external crosstalk Transition windows at ports Transition windows for potential aggressors or sensitive nets
14 Juan-Antonio Carballo EDP 2004 Supply and Ground Grid Noise & Electromigration Electrical data Electrical data Specification Power Model Requirements Physical data Geometrical data of supply nets Timing data Variation in pin timing (delay, slew, setup, hold) from IR drop Other Multiple supplies for analog blocks, multi Vt circuits, pads
15 Juan-Antonio Carballo EDP 2004 Substrate Noise and Coupling Electrical data Block-level impedance model Physical data Regions Noise sources, aggressor ports Max noise for victim port Substrate access ports
16 Juan-Antonio Carballo EDP 2004 Impact on Flow System- and chip-level design ½-custom digital Custom analog Custom digital RTL / Logic Behavior Circuit Layout Physical Synthesis Circuit Layout Characterization Physical Characterization Manufacturing Verification/ integration Mask prep, Manufacturing
17 Juan-Antonio Carballo EDP 2004 An Electrical Phenomenon! Types of SI SoC Task Deliverables physical 20% logical 4% timing 15% electrical 61%
18 Juan-Antonio Carballo EDP 2004 Crosstalk A Key Concern! Types of SI SoC Task Deliverables " based on the SI phenomenon they address Supply and ground 15% Electromigrat ion 15% Substrate coupling 11% Signal crosstalk 59%
19 Juan-Antonio Carballo EDP 2004 Standard Reuse in SoC Methodology! Formats/interfaces referred to in VSIA SI specification More than 50% existing standards PDEF 11% GDSII 2% LEF 2% SPEF 11% Document 45% Spice-like 29%
20 Juan-Antonio Carballo EDP 2004 Impact on Flow System- and chip-level design ½-custom digital Custom analog Custom digital RTL / Logic Behavior Circuit Layout Physical Synthesis Circuit Layout Characterization Physical Characterization Manufacturing Verification/ integration Mask prep, Manufacturing
21 Juan-Antonio Carballo EDP 2004 Impact on Early Exploration! Chip partitioning sub-flow " key for SoC " Determines wiring = electrical SI " Need to use standard SI block info! Analog-digital division line " fundamental in signal integrity management "if actual spatial partitioning is done " Functional division into A/D has strong influence on SI "analog circuits tend to be more sensitive.
22 Juan-Antonio Carballo EDP 2004 Impact on Flow System- and chip-level design ½-custom digital Custom analog Custom digital RTL / Logic Behavior Circuit Layout Physical Synthesis Circuit Layout Characterization Physical Characterization Manufacturing Verification/ integration Mask prep, Manufacturing
23 Juan-Antonio Carballo EDP 2004 Impact on RTL / Logic! On synthesis SI increases need to accommodate electrical effects surge of SI effects near 100 nm primary focus of SI embedding in the design flow! Example " crosstalk and supply noise Strong influence on delay Modern synthesis intimately related to timing SI a primary factor to account for
24 Juan-Antonio Carballo EDP 2004 Impact on Flow System- and chip-level design ½-custom digital Custom analog Custom digital RTL / Logic Behavior Circuit Layout Physical Synthesis Circuit Layout Characterization Physical Characterization Manufacturing Verification/ integration Mask prep, Manufacturing
25 Juan-Antonio Carballo EDP 2004 Impact on Circuit! Impact of SI is obvious " SI is primarily a circuit-level phenomenon " Characterization fundamental flow path for SI info! Analog Circuit topology and power increasingly important Raised in analog sub-flow of AMS design methodologies
26 Juan-Antonio Carballo EDP 2004 Impact on Flow System- and chip-level design ½-custom digital Custom analog Custom digital RTL / Logic Behavior Circuit Layout Physical Synthesis Circuit Layout Characterization Physical Characterization Manufacturing Verification/ integration Mask prep, Manufacturing
27 Juan-Antonio Carballo EDP 2004 Impact on Layout! Most of the SI impact can be classified as embedding of isolation techniques in the design flow Increasingly common in mixed-signal purely digital designs
28 Juan-Antonio Carballo EDP 2004 Impact on Flow System- and chip-level design ½-custom digital Custom analog Custom digital RTL / Logic Behavior Circuit Layout Physical Synthesis Circuit Layout Characterization Physical Characterization Manufacturing Verification/ integration Mask prep, Manufacturing
29 Juan-Antonio Carballo EDP 2004 Impact on Chip Integration! Renewed importance Due to rise of system-on-chip design Key techniques 1. Floorplanning 2. Isolation
30 Juan-Antonio Carballo EDP 2004 Conclusions! Signal integrity First-order concern in System-on-a-Chip (SoC) design! SoC methodologies need to be fundamentally transformed Must develop techniques to enhance block reuse while accounting for signal integrity! Reuse standards work can achieve this goal Virtual Socket Interface Alliance (VSIA) " focus on reuse Signal Integrity (SI) sub-working group focus on SI in SoC Work integrates with SoC methodologies, enhances block reuse
31 Juan-Antonio Carballo EDP 2004 Back-up Slides
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