Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng

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1 Architectural Level Power Consumption of Network Presenter: YUAN Zheng

2 Why Architectural Low Power Design? High-speed and large volume communication among different parts on a chip Problem: Power consumption Many methods : physical level, circuit level, system level One important aspect: Architectural Level 2

parts on a chip Problem: Power consumption Many methods :

3 Outline 1. Introduction 2. Energy-Efficiency for Interconnection 3. Power Consumption of Switching and Routing 4. Example: MAIA 5. Summary 3

4 Outline 1. Introduction 2. Energy-Efficiency for Interconnection 3. Power Consumption of Switching and Routing 4. Example: MAIA 5. Summary 4

5 NoC Architecture Shared Medium Networks Single Bus Network Multiple Bus Network Direct and Indirect Network Switch and Route Infrastructure Hybrid Network Hierarchical and Heterogeneous Architecture 5

Indirect Network Switch and Route Infrastructure

6 Hierarchical and Heterogeneous Architecture Locality reduces the cost of global connections Wiring channels created along the sides of each module Switchbox Generalized mesh structure 6

7 Outline 1. Introduction 2. Energy-Efficiency for Interconnection 3. Power Consumption of Switching and Routing 4. Example: MAIA 5. Summary 7

8 Architectural Effect on Power Consumption 50 % from interconnect wires Short range local communication fast and power efficient Long range global communication complex protocol slow and power inefficient * D. L. Liu and C. Svensson, Power consumption estimation in CMOS VLSI chips, IEEE Journal SSC, June

communication complex protocol slow and power inefficient * D. L. Liu and C.

9 Power Dissipation of Bus Structure Poor in energy efficiency because each data transfer is broadcast Load capacitance of the entire bus has to be driven during each data transfer P = 1/2 C f V 2 Load capacitance 9

Load capacitance of the entire bus has to be driven

10 Bus Splitting Split bus into multiple segments Data transfers proceed in parallel locally High throughput and low energy consumption 10

11 Clustering Partition the modules into clusters of tightly-connected components Elements (cores) share physical communication channels More power efficient in intracluster Balance communication load Hierarchical generalized mesh 11

physical communication channels More power efficient in

12 GALS - Globally Asynchronous Locally Synchronous Partition system into optimal number/size of synchronous blocks Communicate asynchronously Clock frequency Power consumption 12

13 Outline 1. Introduction 2. Energy-Efficiency for Interconnection 3. Power Consumption of Switching and Routing 4. Example: MAIA 5. Summary 13

14 Switch and Router Banyan switch Router-based architecture 14

15 Power Modeling for Switching (1) The power consumption on switch fabrics comes from three different sources: 1. Internal node switches 2. Internal buffer queues 3. Interconnect wires 15

16 Power Modeling for Switching (2) Bit Energy E bit : Energy consumed for each bit when the bit is transported inside the switch fabrics from ingress ports to egress ports 1. Internal node switches : E Sbit 2. Internal buffer queues : E Bbit 3. Interconnect wires : E Wbit * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

Internal node switches : E Sbit 2. Internal buffer queues : E Bbit 3.

17 Node Switch Power Consumption E Sbit Packets from one stage to the next stage Header data path and payload data path E Sbit is input state-dependent Input vector 0 1 switch * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

vector 0 1 switch * Ye, T.T.; Benini, L.; De Micheli, G.

18 Internal Buffer Power Consumption E Bbit Destination contention two or more packets in the ingress ports requesting the same destination port at the same time Interconnect contention same interconnect link may be shared by packets with different destinations * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

interconnect link may be shared by packets with different destinations * Ye, T.T.; Benini, L.

19 Interconnect Wires Power Consumption E Wbit Signal on the wire will toggle between logic 0 and logic 1 C wire : wire capacitance C input : total capacitance of input gates C W = C wire + C input : total load capacitance * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

wire + C input : total load capacitance * Ye, T.T.; Benini, L.; De Micheli, G.

20 Interconnect Wire Length Estimation Thompson Model Based on graph embedding process Each vertex in G is mapped into a d d square of vertices in H, where d is the degree of vertex Each edge in G is mapped into one or more edges of graph H Find the minimum number of columns p min and rows q min in H G(V G,E G ) H(V H,E H ) V: Vertices E: Edges d = 4 ->

Each edge in G is mapped into one or more edges of graph H Find the minimum number of

21 Switch Architecture Purpose : compare the power consumption in different switch architectures A. Crossbar Switch B. Full Connected Network C. Banyan Network D. Batcher Banyan Network 21

22 A. Crossbar Switch Any of the N input ports can be connected to any of the N output ports by a node switch Interconnect contention free Destination contention free (solved by arbiter, no buffer need) Bit energy of thompson grid wire * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

23 B. Full-Connected Network Arbiter controls MUXs to direct the switch path Interconnect contention and Destination contention free Power consumption and complexity scale up with the number of inputs N * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

24 C. Banyan Network Butterfly topology: N = 2 n inputs and N = 2 n outputs Stage i checks the i th bit of the destination address of the packet, self-routing switch fabric, buffer used for Interconnect contention problem Bit energy of thompson grid wire q i = 1 : contention occurs q i = 0 : no contention * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

25 D. Batcher Banyan network Similar to Banyan network Solve interconnect contention problem Sorting network added, each input-output connection have its own dedicated path bit energy of sorting switches * Ye, T.T.; Benini, L.; De Micheli, G. Analysis of power consumption on switch fabrics in network routers Design Automation Conference,

26 Analysis of the Switch Network Architecture I. Fully connected switch has the lowest power consumption, but large implementation area and less flexibility. II. Interconnect contention has a dramatic impact on the power consumption of Banyan switch because of buffer problem. III. Interconnect wires dominate the power consumptions with large switch port. 26

27 Outline 1. Introduction 2. Energy-Efficiency for Interconnection 3. Power Consumption of Switching and Routing 4. Example: MAIA 5. Summary 27

28 Voice Coding Chip - MAIA Programmable microprocessor Heterogeneous computing elements (satellite) Two-level hierarchical meshstructure with reconfigurable interconnect network Architecture of MAIA Voice Coding Chip 28

29 Component Description Embedded Microprocessor Power and performance optimized ARM8 core Programmable ASIC Elements Dual-stage pipelined MAC(multiply-accumulate) and ALU Embedded FPGA Logic block Low-swing circuits Interconnect Architecture Clock Distribution 29

30 Reconfigurable Interconnect Architecture Reconfiguration model The bars (C1, C2, etc.) between two reconfiguration times (t0->t1, t1->t2) represent a set of intersatellite connections realized simultaneously by the reconfigurable interconnect. 30

31 Communication Interface Description Inter-Satellite Communication Interface two-phase self-timed handshaking scheme, realized in a globally asynchronous, locally synchronous implementation (GALS) fashion. Communication Interface Between Microprocessor and Satellites Synchronization and communication between synchronous ARM8 core and asynchronous reconfigurable data paths using interface control unit 31

32 Hierarchical Generalized Mesh Interconnect Network Four clusters of tightly connected modules Each cluster has a local mesh for intra-cluster connections Interface ports for intercluster connection as hierarchical switch-boxes Interface for Microprocessor and Satellites Inter-cluster communication Switch box Intra-cluster communication Hierarchical 2-level generalized mesh architecture (LAYOUT) 32

33 Result Model-to-model energy of different architectures Manhattan Distance : shortest distance between two points measured along X and Y axes * H. Zhang, "A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications", IEEE Journal on Solid State Circuits, Vol. 35, Nov

34 Outline 1. Introduction 2. Energy-Efficiency for Interconnection 3. Power Consumption of Switching and Routing 4. Example: MAIA 5. Summary 34

35 Summary 1. Bus-based network : poor power efficiency and limited throughput, but simple and economical 2. Switch and route : great high performance and low power efficiency, but complex and variable 3. Power dissipation on buffers increases sharply as throughput increases in switch architecture 4. Interconnect wires dominate the power consumptions with large switch port 5. MAIA, a voice chip, implemented with hierarchical and heterogeneous architecture is much more energy efficient 35

36 Thank you for your presence! QUESTIONS

Design and Implementation of an On-Chip timing based Permutation Network for Multiprocessor system on Chip

Design and Implementation of an On-Chip timing based Permutation Network for Multiprocessor system on Chip Ms Lavanya Thunuguntla 1, Saritha Sapa 2 1 Associate Professor, Department of ECE, HITAM, Telangana