Agenda. Michele Taliercio, Il circuito Integrato, Novembre 2001

Transcription

1 Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28

2 How to handle complexity G The engineering approach: Ø break a complex problem into smaller parts, and solve one problem at a time. G To reduce design complexity: use a hierarchical approach and move the problem to higher abstraction levels, until the complexity becomes manageable. G At each level, what is needed is: Ø a way of modeling the single blocks Ø tools and methodology to analyze the relations among the blocks??? 29

3 System Design Stages CUSTOMER S REQUIREMENTS SYSTEM SPECIFICATIONS HARDWARE DESIGN ARCHITECTURE DEFINITION SOFTWARE DESIGN 30

4 Capturing the Requirements REQUIREMENTS FROM CUSTOMER S WISHES TO.. SPECIFICATION A COMPLETE DESCRIPTION OF THE BEHAVIOUR OF THE SYSTEM WRITTEN IN A LANGUAGE THAT CAN BE SIMULATED EXECUTABLE SPECIFICATION IMPLEMENTED AS A WORKING MODEL ON A COMPUTER OR ON A BOARD VIRTUAL PROTOTYPE 31

5 Virtual Prototyping SW DEVELOPMENT ARCHITECTURE DEFINITION HW DESIGN SILICON FAB. SW DEBUG FINAL PRODUCT Virtual prototyping allows the parallel development of software and hardware in a concurrent mode. Applications can be debugged even before the silicon is available SW DEVELOPMENT SW DEBUG ARCHITECTURE DEFINITION VIRTUAL PROTOTYPE FINAL PRODUCT HW DESIGN SILICON FAB. 32

6 Mapping behaviors BEHAVIORAL DESCRIPTION ARCHITECTURAL DESCRIPTION µp RAM DSP Functions MAPPING Resources µp RAM DSP Implementing functions with available resources 33

7 Implementing the functions Basic design functions can be implemented either in Hardware or in Software HARDWARE +FASTER + LESS POWER + LESS SILICON AREA + EASIER TO VERIFY SOFTWARE + MORE FLEXIBLE + EASILY PORTABLE + CAN BE UPDATED + LAST MINUTE UPGRADE + PLATFORM RE-USE The choice between the type of implementation for each block, is the key to design success, and must be supported by a careful alternative analysis 34

8 The lowest design layers RTL (Register Transfer Level) Gate Transistor Layout 35

9 RTL-to-Layout Design Flow RTL circuit description Synthesis Placement Parasitic load based on statistical wire load estimation Multiple iterations Extracted timing data Routing Parasitic Extraction and Timing Analysis NO Timing Closed? Timing computed on real loads, extracted from layout YES 36

10 Synchronous Design A basic assumption behind the logical synthesis is that the design is synchronous. A timing signal (clock) is distributed through all the circuit, and the status of the signals is sampled only at discrete intervals Underlying assumptions: The time between two clock pulses is long enough, to allow the internal nodes to reach the final state; The clock signal is simultaneous in all the circuit Standard logical synthesis tools are working ONLY with synchronous design, but: With the increase in clock speed and in interconnection delays, the basic physical assumptions are no longer valid 37

11 Power Reduction Strategies IMPACT SIMULATION TIME Architecture Algorithms, HW/SW partitioning, SW optimization, SW compilers 100x Behavioral Resource scheduling and allocation, concurrency RTL Clock gating, multiple voltages, asynchronous design Circuit Low power libraries, technology mapping, optimized sizing Technology Multiple Vt, transistor optimization, low k dielectric., SOI, triple well. 10x 2x 38

12 Verification Flow BEHAVIOUR BEHAVIOUR TO TO BE BE CHECKED CHECKED GENERATION GENERATION OF OF TEST TEST SIGNALS SIGNALS SIMULATION SIMULATION COMPARE COMPARE WITH WITH EXPECTED EXPECTED RESULTS RESULTS Simulation is supposed to cover critical behaviors, but only a limited number of cases can be checked. Problems: Which is the test coverage? What about unexpected configurations? How many duplication? Are there configurations which are never checked? 39

13 Verification Strategies Logical verification is performed by reproducing the structure of the design (at RTL level or gate level) on a proper platform: SW simulation program on a workstation or PC HW assembly of FPGA s, processors and standard components OBSERVABILITY SW SIMULATORS HW EMULATORS FPGA BOARDS 1 1K 1M CLOCK FREQUENCY [Hz] 40

14 Formal Verification Testing all possible configurations of a circuit can require more than the age of Universe. Formal verification aims at analyzing the formal characteristics of a design, instead of checking the response to a set of stimuli. Offers a 100% coverage, but at the moment is limited to small blocks, and cannot cover all classes of circuits. Property checking: verifieshw architecture against specifications Equivalence checking: verifyiftwo different implementations of a circuit are equivalent Transistor abstraction: providesa logic model from a transistor-level description 41

15 Asynchronous Design It is more and more difficult to guarantee a proper clock distribution Signal propagation does not match increase in clock frequency Clock toggling is one of the major sources of noise and power dissipation WHY NOT GET RID OF CLOCKS? An asynchronous design requires that all propagation delays are taken properly into account. However no tools and no automatic design flow are available yet 42

16 Interfacing the world Courtesy of CADENCE Design does not stop at the pads Package is becoming an active part of the IC device: Multilevel interconnections inside the package Multichip packaging Passive device integration Package design will become a part of IC design, and tools are needed to interface the two worlds. 43

17 Growing Mask Costs 2?? MaskSetCost[M$] Technology Generation [µm]

18 Platform-based Design The cost of mask sets keeps increasing, because of higher mask count and manufacturing complexity. WHY NOT TO USE A SINGLE PLATFORM FOR SEVERAL APPLICATIONS? control & low volume data processing µp + massive data processing DSP + reconfigurable glue logic FPGA = GENERIC ASIC PLATFORM + Cache, buffer SRAM G but HOW MUCH PERFORMANCES ARE WE READY TO TRADE OFF FOR STANDARDIZATION? 45