Digital Integrated Circuit (IC) Layout and Design

Transcription

1 Digital Integrated Circuit (IC) Layout and Design! EE 134 Winter 05 " Lecture Tu & Thurs. 9:40 11am ENGR2 142 " 2 Lab sections M 2:10pm 5pm ENGR2 128 F 11:10am 2pm ENGR2 128 " NO LAB THIS WEEK " FIRST LAB Friday Jan. 20 EE134 1 People! Lecturer - Roger Lake " Office ENGR2 Rm. 437 " Office hours - MW 4-5pm " rlake@ee.ucr.edu! TA FarukYilmaz " Office ENGR2 Rm. 222 " Office Hours TBD " faruk@ee.ucr.edu EE134 2

2 EE134 Web-site! " Class lecture notes " Assignments and solutions " Lab and project information " Exams and solutions " Other useful links EE134 3 Class Organization! Homework assignments (10%)! Labs (20%) " Tutorials to learn the Cadence design software! Final Project (50%) " Design a digital circuit (eg. 4 bit adder) " Work in teams of 3! Midterm (20%) EE134 4

3 Text Book Digital Integrated Circuits: A Design Perspective, 2 nd Ed. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic EE134 Software! Cadence software " Online documentation and tutorials " Sun4 UNIX Workstations EE134 6

4 What is this book all about?! Introduction to digital integrated circuits. " CMOS devices and manufacturing technology. " CMOS inverters and gates. " Propagation delay, " noise margins, and " power dissipation. " Sequential circuits. Arithmetic, interconnect, and memories.! What will you learn? " Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability EE134 7 Digital Integrated Circuits! Introduction: Issues in digital design! CMOS devices and manufacturing! The CMOS inverter! Combinational logic structures! Propagation delay, noise margins, power! Sequential logic gates; timing! Interconnect: R, L and C! Arithmetic building blocks! Memories and array structures! Design methods EE134 8

5 EE134 Winter Lecture 1! Introduction EE134 9 Introduction! Why is designing digital ICs different today than it was before?! Will it change in future? EE134 10

6 The First Computer (1832) The Babbage Difference Engine (1832) 25,000 parts cost: 17,470 EE ENIAC - The first electronic computer (1946) EE134 12

7 The Transistor Revolution First transistor Bell Labs, 1948 EE The First Integrated Circuits Bipolar logic 1960 s ECL 3-input Gate Motorola 1966 EE134 14

8 Intel 4004 Micro-Processor (1971) ,300 transistors 108 KHz operation EE Intel Pentium 4 microprocessor (2000) 42 M transistors (217 mm 2 ) 1.5 GHz 0.18 µm 180 nm technology node EE134 16

9 What Happened over 30 Years? ,300 transistors 108 KHz operation ~ 15,000 x 42 M transistors 1.5 GHz operation Automotive comparison: SF to NY in 13 seconds. EE Moore s s Law # In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. # He made a prediction that semiconductor technology will double its effectiveness every 18 months EE134 18

10 Moore s s Law LOG 2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION Electronics, April 19, EE Evolution in Complexity EE134 20

11 Transistor Counts 1,000,000 K 1 Billion Transistors 100,000 10,000 1, Pentium III Pentium II Pentium Pro i486 Pentium i Source: Intel Courtesy, Intel Projected EE Moore s s law in Microprocessors Transistors (MT) X growth in 1.96 years! P6 Pentium proc Year Transistors on Lead Microprocessors double every 2 years Courtesy, Intel EE134 22

12 Die Size Growth 100 Die size (mm) P6 486 Pentium proc ~7% growth per year ~2X growth in 10 years Year Die size grows by 14% to satisfy Moore s Law Courtesy, Intel EE Frequency Frequency (Mhz) Doubles every 2 years P6 Pentium proc Year Lead Microprocessors frequency doubles every 2 years Courtesy, Intel EE134 24

13 Power Dissipation 100 Power (Watts) P6 Pentium proc Year Lead Microprocessors power continues to increase Courtesy, Intel EE Power will be a major problem Power (Watts) Pentium proc 18KW 5KW 1.5KW 500W Year Power delivery and dissipation will be prohibitive Courtesy, Intel EE134 26

14 Power density Power Density (W/cm2) Rocket Nozzle Nuclear Reactor 8086 Hot Plate P6 Pentium proc Year Power density too high to keep junctions at low temp Courtesy, Intel EE Not Only Microprocessors Cell Phone Small Signal RF Power RF Power Management Digital Cellular Market (Phones Shipped) Analog Baseband Digital Baseband (DSP + MCU) Year Units (M) (703) (776) (836) (889) EE134 28

15 Challenges in Digital Design (# Transistors) 1/(Transistor size) Microscopic Problems Ultra-high speed design Interconnect Noise, Crosstalk Reliability, Manufacturability Power Dissipation Clock distribution. Everything Looks a Little Different? Macroscopic Issues Time-to-Market Millions of Gates High-Level Abstractions Reuse & IP: Portability Predictability etc. and There s a Lot of Them! EE Productivity Trends 10,000,000 10,000 1,000,000 1, , , , Logic Tr./Chip Tr./Staff Month. x x x x x x x x 58%/Yr. compounded Complexity growth rate 21%/Yr. compound Productivity growth rate 100,000,000 10,000,000 1,000, ,000 10,000 1, Complexity Logic Transistor per Chip (M) Productivity (K) Trans./Staff - Mo Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap EE134 30

16 Why Scaling?! Technology shrinks by 0.7/generation! With every generation can integrate 2x more functions per chip; chip cost does not increase significantly! Cost of a function decreases by 2x! But " How to design chips with more and more functions? " Design engineering population does not double every two years! Hence, a need for more efficient design methods " Exploit different levels of abstraction EE Design Abstraction Levels SYSTEM + MODULE GATE CIRCUIT S n+ G DEVICE n+ D EE134 32

17 Next Class! Introduce basic metrics for design of integrated circuits how to measure delay, power, etc.! Introduction to IC manufacturing and design. EE EE134 34