Systematic Design for a Successive Approximation ADC

Transcription

1 Systematic Design for a Successive Approximation ADC Mootaz M. ALLAM M.Sc Cairo University - Egypt Supervisors Prof. Amr Badawi Dr. Mohamed Dessouky

2 2 Outline Background Principles of Operation System and Circuit Design Case Study Simulations Layout Generation Performance Evaluation Conclusion Perspectives

3 3 The Successive Approximation ADC «The Return» Moderate Resolution Low Power Minimum Active blocs Reconfigurable Emerging new Applications MEMS Sensor Interface: Resolution: 7-8 bits, BW=50kHz [Scott 2003] Multi-standards RF receiver Resolution: 8 bits, BW = 20 MHz [Montaudon 2008] Ultra Wide Band (wireless UWB): Resolution: 5-6 bits, BW=300MHz [Chen 2006]

4 4 Figure of Merit FOM P Resolution 2 *2* BW

5 5 Objectives Develop a systematic design method for successive approximation ADC from system to layout level. Develop a general simulation environment with different levels of abstraction and programmed performance analysis. Emphasis on analog design automation and reuse techniques: Automatic sizing Layout generation Optimizing Layout for best matching

6 6 Principle of Operation Comp MSB LSB V V V V in b b b b REF REF REF REF

7 7 Outline Background Principles of Operation System and Circuit Design Case Study Simulations Layout Generation Performance Evaluation Conclusion Perspectives

8 8 Single Ended SAR-ADC. sample V REF REF 8C 4C 2C C C Clock sample v in V REF 2 V REF

9 9 Sampling Mode REF sample VDAC V REF Clock sample invert 8C 4C 2C C C Clock sample vvin in VDAC V REF VIn V REF 2 V Ref

10 10 Inversion Mode V REF VDAC = v IN V REF Clock sample invert 8C 4C 2C C C Clock gnd invert VDAC V REF v IN V REF vin

11 11 Charge redistribution mode (MSB) V REF vin VDAC= V REF 2 V REF Clock sample invert 8C 4C 2C C C Clock VDAC V REF V REF 8C V 2 REF 8C V INITIAL V REF V REF 2 1

12 12 Charge redistribution mode (MSB-1) V REF VDAC = VREF V vin 2 4 REF V REF 8C 4C 2C C C Clock Clock sample invert VDAC V REF V REF 4C V 4 REF V INITIAL V REF V REF 4 12C 1 0

13 13 Mode Redistribution de la charge (MSB-2) V REF VDAC = VREF V vin 2 8 REF V REF 8C 4C 2C C C Clock Clock sample invert V REF V REF VDAC V REF V REF 8 V V V V Vin b b b b REF REF REF REF

14 14 Mode Redistribution de la charge (LSB) V REF VDAC = V V V v IN REF REF REF V REF 8C 4C 2C C C Clock Clock sample invert V REF V REF VDAC V REF V REF 16 V V V V Vin b b b b REF REF REF REF

15 15 Problem Selecting V dd V dd V REF V dd Sometimes VDAC Vdd To increase the dynamic range V dd Leakage when using normal PMOS switch. 8C 4C 2C C C Clock V dd V dd V dd VDAC V dd Possible Solution: Switched charge-pump [scott03] or Bootstrap [dessouky01]

16 16 Possible solutions - Leakage Bootstrap Switch Charge pump Switch VDD VDAC VDAC 0 < VDAC < 1.5 VDD Reliability problem Since sometimes VDAC value=1.5 VDD While VG1 = 0 when M1 is ON, VGD,M1 exceeds VDD

17 17 Possible solutions - Reliability Max OFF = VDD - Vtn 0 < VDAC < 1.5 VDD Shielding Switch

18 18 Possible solutions - Circuitry Bootstrap [dessouky01] Modified Shielding Bootstrap

19 19 Differential SAR-ADC V dd 2 V dd 4C 2C C C v in 2 V dd 2 V dd 2 sample Triple Reference 4C 2C C C Clock sample v in 2 V dd 2 V dd

20 20 Differential SAR-ADC V dd 4C 2C C C V dd vin V dd V dd V dd V dd vin V dd V dd V dd C 2C C C V dd 2 Clock Clock sample invert V dd In1 DAC2 V dd 2 DAC1 V dd V dd V dd 2 In

21 21 Operation Summary Single Ended Double reference Differential Triple reference 2 times the numbers of capacitors 6 times the numbers of switches Special Switch (charge-pump - bootstrap) Lower power consumption No need for special switch Differential architectures advantages : - Suppressing even harmonics -Common mode rejection -Offset removal Better performance at high frequencies

22 22 Outline Background Principles of Operation System and Circuit Design Case Study Simulations Layout Generation Performance Evaluation Conclusion Perspectives

23 23 Design - Architecture Clock In Capacitor array Switches Comp Control SAR Switches Control Sample invert

24 24 Capacitor array design issues - Noise kt 1- Thermal noise [ ], due to Sampling C TOT V dd sample V dd v in R Switch 8C 4C 2C C C Clock CTOT 16C sample v in V dd C increases, thermal noise decreases Unit

25 25 Capacitor array design issues - Mismatch 2 Capacitor Mismatch (Introduced in fabr ication) - Affects Generated comparison levels of the capacitve DAC V dd 8( C C) 8C V dd 2 C increases, mismatch effect decreases Unit

26 26 Capacitor array design issues - f Sampling 3- Sampling Frequency v in R Switch Clock R C Switch Total CTOT 16C sample V dd t sampling T Clock 2 For an accurate sampling C decreases, bandwidth increases Unit

27 27 Switches 1) Switches selection NMOS to switch Vgnd and Vcm PMOS to switch Vdd CMOS to switch Vin Bootstrap to force deep off-state of critical switches 2) Sizing switches (compromise) Increasing W/L reduces Rswitch and so, on the account of increasing switch parasitcs. In the used DAC, this will be of minor importance if operating in low frequency because the switches are all connected to the bottom plates

28 28 Design - Architecture Clock In Capacitor array Switches Comp Control SAR Switches Control Sample invert

29 29 Comparator Circuit Reset to Vdd h MP9 MP7 MP8 MP11 h Qm Qp Cuts the current path in the RESET phase h MN5 MN6 h Input Signal ep MN1 MN3 MN4 MN2 em Latch

30 30 Comparator Operation phases Reset phase to Vdd Comparison phase Inputs Latch starts Resolution > V LSB 2 Response time < 0.5 T H

31 31 Comparator Design tradeoff Sizing input pair and latch latch init ITotal V offset Improve with decreasing L Improve with increasing L Tradeoff

32 32 Design - Architecture Clock In Capacitor array Switches Comp Control SAR Switches Control Sample invert

33 33 SAR algorithm - Implementation LFSR: Linear Feedback Shift Register DAC outputs C X a8 2 a a7 3 a8 a a6 4 a8 a7 a a5 5 a8 a7 a6 a a4 6 a8 a7 a6 a5 a a3 7 a8 a7 a6 a5 a4 a3 1 0 a2 8 a8 a7 a6 a5 a4 a3 a2 1 a1

34 34 Systematic design for SA-ADC Resolution BW Power - Techno Non idealities and noise Thermal noise, mismatch, Clock frequency Comparator specs Settling, resolution, kickback. System architecture DAC topology, SAR algorithm, Sampling technique Switches Sizing Select number of stages Cmin Cmax Sizing procedure No Cmax >Cmin No No Check Specs No Yes C unity = C min Yes Finalize design Layout

35 35 Outline Background Principles of Operation System and Circuit Design Case Study Simulations Layout Generation Performance Evaluation Conclusion Perspectives

36 36 Case Study Case Study Differential Architecture Resolution: 8bit BW: 50 KHz F clock : 1MHz Technology: 0.13u ST, MIM Capacitors Verification VHDL AMS used for verification with simulation Different levels of abstraction (Behavioral, gates, transistor, ) Mixed blocs simulation (Analog / Digital)

37 37 Multiple abstractions Macro model Transistor MIM Macro model Macro model Transistor VHDL In Capacitor array Switches Comp + Latch Control Transistor Clock gen VHDL

38 38 Verification Environment Abstraction level Ideal, mismatched, techno, Type of analysis Component sizes Resolution BW Verification Environment presets DAC topology, SAR algorithm, Sampling technique Sketch output spectrum Calculate SNDR Sketch SNDR v.s. fin Sketch SNDR v.s. Ain Sketch INL and DNL Sketch Transient response at each node

39 39 Transiant Single Ended - Output Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V Transistor level simulations

40 40 Transiant Differential - Output Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V Transistor level simulations

41 41 Transiant Differential - DACs Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V Differential DACs output Transistor level simulations

42 42 Transiant Differential - Comparator Vdd 1.2V Full conversion: Differential DACs output Comparator output Transistor level simulations Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V

43 43 Transient SAR control Control block turning ON and OFF DAC switches [case of 0 input] VHDL Description Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V

44 44 Transient Full Scale Ramp Full Scale Slow ramp excitation Zoom - in Vinp-p 1.2V

45 45 Static Performance - Transistor Level Static performance Evaluation in (LSB): DNL and INL [16 sample / bin]

46 46 Dynamic Performance Ideal Models Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V Ideal models simulation 4096 point FFT SNDR = db

47 47 Dynamic Performance Mixed Models Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V Ideal SNDR = db MOS switches SNDR = db 4096 point FFT MOS comparator 0.01 mismatch in Cu SNDR = db SNDR = db

48 Power Specral Density (db) 48 Dynamic Performance Transistor Level Vdd 1.2V Fin 1.4KHz Fclk 1MHz Transistor level simulations 1024 point FFT SNDR = 46.2 db Frequency (Hz)

49 Signal to noise and distortion ratio SNDR(dB) 49 Dynamic Performance Vdd 1.2V Fin 1.4KHz Fclk 1MHz Transistor level simulations SNDR max Ideal =47.47 db Transistor Level = point FFT Amplitude of input signal(db)

50 Signal to noise and distortion ratio SNDR(dB) 50 Dynamic Performance Vdd 1.2V Transistor level simulations Fclk 1MHz Vinp-p 1.2V 4096 point FFT BW =55 KHz Frequency of input signal (Hz)

51 51 Mismatch analysis Vdd 1.2V Fin 1.4KHz Fclk 1MHz Vinp-p 1.2V 0.05 mismatch in Cu SNDR = db 0.1 mismatch in Cu SNDR = db 4096 point FFT

52 52 Layout generation for SA-ADC Comparator transistor sizes Design phase Desired layout shape Number of capacitors and sizes Unit capacitance Common centroid placement algorithm Layout template s -Component connectivity -Relative place and route CAIRO Layout generation Target technology DRC LVS Parasitics Ext. Verification Fabrication

53 Layout Comparator - Floorplan 53

54 54 Layout Comparator - Generated Area 22 x 39 µm 2 Dummies Removed for Layout verification

55 55 Layout Differential DACs - Floorplan Common centroid placement for 16 capacitor

56 56 Layout Differential DACs - Generated Layout Cu Placed and Routed Area 1.26 x 0.26 mm 2 and Huge routing parasitics

57 57 Layout Differential DACs - Manual Layout Cu Placed and Routed 2/3 less routing parasitics Area mm 2 ZOOM

58 58 Performance [Hong07] This work* [scott03] Technology 0.18 µm 0.13 µm 0.25 µm Supply 0.83 V 1.2 V 1.0 V Input range Rail to Rail Rail to Rail Rail to Rail Sampling rate 111 KHz 111 KHz 100 KHz Unit Cap. 24 ff 30fF 12f Power (Analog) 1.16 µw 0.72µW 2.2 µw Area mm mm mm2 SNDR@BW db 46.2dB 43.8 db Architecture Single Ended Differential Single Ended FOM 65 fj/bit 64fJ/bit 2163 fj/bit

59 59 Outline Background Principles of Operation System and Circuit Design Case Study Simulations Layout Generation Performance Evaluation Conclusion Perspectives

60 60 Summary and Conclusion Systematic design methodology for SA-ADC from system to layout. General simulation environment Different abstraction levels. Different verification tests. Emphasis on analog design automation and reuse Optimizing Layout for best component matching Verification with case study for WSN specs

61 61 Perspectives Targeting high frequency specs (>500 Msample/S) Redundant system error correction code [Kuttner02] Digital calibration [Promitzer01] Asynchronous operation [Chen06] Time interleaving [Chen06] Full Automation Sizing procedure with layout parasitics awareness Layout generation for the full ADC

62 Thank You 62