EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 16 Timing and Clock Issues

Transcription

1 EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 16 Timing and Clock Issues 1 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on timing Clock distribution 2 1

2 Clocked Synchronous State Machine Flip-Flop Timing Parameters 2

3 Latch Timing Parameters State Machine Timing 3

4 Satisfying Timing Requirements The period must be long enough for the data to propagate through the registers and logic and to be set up at the destination register before the next rising edge of the clock. Satisfied by making T long enough. Cycle time: T CLK > t c-q + t logic + t su The hold time at the destination register must be shorter than the minimum propagation delay through the logic network. This requirement is independent of system clock; manufacturer s minimum delay specifications are needed. Guarantee that minimum combinational logic delay is larger than hold time. Race margin: t hold < t c-q,cd + t logic,cd Clock Uncertainties Devices 2 4 Power Supply 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines 4

5 Clock Nonidealities Clock Skew Spatial variations in equivalent clock edges Mostly deterministic Clock Jitter Temporal variations in consecutive clock edges Mostly random Pulse Width Variation Clock Skew and Clock Jitter Clk t SK Clk t JS Clock skew and jitter can affect the cycle times Clock skew can cause race conditions 5

6 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on timing Clock distribution Clock Skew Bad design 6

7 Clock Skew Clock Skew In R1 D Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c - q t c - q, cd t su, t hold t logic t logic, cd Assume the following timing parameters are available: Contamination or minimum delay (t c-q,cd ) and maximum propagation delay (t c-q ) of the register Setup (t su ) and Hold (t hold ) times for registers Contamination delay (t logic,cd ) and maximum delay (t logic ) of the combinational logic The positions of the rising edges of clocks CLK1 and CLK2 (t CLK1 and t CLK2 ) relative to a global reference. Ideally t CLK1 = t CLK2. 7

8 Positive Clock Skew Launching edge arrives before the receiving edge Minimum clock cycle: T+ t c-q + t logic + t su In CLK D R1 Q t CLK1 Combinational Logic R2 D Q t CLK2 t c - q t c - q, cd t su, t hold t logic t logic, cd Negative Clock Skew Receiving edge arrives before the launching edge Minimum clock cycle: T+ t c-q + t logic + t su In D R1 Q t c - q t c - q, cd t su, t hold t CLK1 Combinational Logic t logic t logic, cd R2 D Q t CLK2 CLK 8

9 Positive and Negative Clock Skew Impact of Clock Skew on Timing: Cycle Time (Long Path) 9

10 Impact of Clock Skew on Timing: Race Margin (Short Path) Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on timing Clock distribution 10

11 Clock Jitter T C LK CLK -t jitter t jitter In REGS CLK t c-q, t c-q, cd t su, t hold t jitter Combinational Logic t log ic t log ic, cd T CLK - 2t jitter t c-q + t logic + t su 2t jitter + t hold < t c-q,cd + t logic,cd Impact of Clock Jitter on Timing: Cycle Time (Late-Early Problem) 11

12 Impact of Clock Jitter on Timing Impact of Clock Skew and Jitter: Cycle Time (Late-Early Problem) 12

13 Impact of Clock Skew and Jitter: Race Margin (Early-Late Problem) Combined Impact of Clock Skew and Jitter Minimum clock cycle (cycle time) T CLK > t c-q + t logic + t su - + 2t jitter Positive skew improves performance Negative skew reduces performance Jitter reduces performance Minimum logic delay (race) t logic,cd + t c-q,cd > t hold + + 2t jitter Skew reduces race margin Jitter reduces acceptable skew Notes: Absolute delay through a clock distribution path is not important What matters is the relative arrival time at the register points at the end of each path 13

14 Overview Sequential system timing requirements Impact of clock skew on timing Impact of clock jitter on timing Clock distribution Dealing with Clock Skew and Jitter Balance clock paths (tree distribution) Don t use gated clocks Use negative skew to eliminate race conditions (at the cost of performance): Add up the components that result in the time budget - the period must be greater than this value T CLK > t c-q + t logic + t su - ( <0) 14

15 Clock Distribution Clock Distribution Distribute clock in a tree fashion H-Tree CLK 15

16 More Realistic H-Trees Example: EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOS 16

17 Spartan-6 FPGA Spartan-6 FPGA Global Clock Network 17

18 Spartan-6 FPGA I/O Clock Network Spartan-6 FPGA Clock Management Tile (CMT) 18

19 Digital Clock Manager (DCM) Eliminating Clock Skew 19

20 Eliminating Clock Skew Quadrant Phase Shifting 20

21 Fine Phase Shifting Summary Clock skew and clock jitter increasingly important issues with technology downscaling CAD tools (e.g., ISE WebPack) take care of many issues automatically 21

22 References and Credits Chapter 10 of: Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, Digital Integrated Circuits, 2nd Edition, Prentice Hall, Spartan-6 FPGA Clocking Resources: _guides/ug382.pdf Appendix A: Asynchronous Inputs 22

23 Asynchronous Inputs: Multiple Synchronizers 23