Digital IC Design Flow

Transcription

1 Collège Militaire Royal du Canada (Cadence University Alliance Program Member) Department of Electrical and Computer Engineering Départment de Génie Electrique et Informatique RMC Microelectronics Lab Cadence Series Digital IC Design Flow A Tutorial on RMC s Digital Design Flow (based on CMOSP18 Artisan) [Version (5.0D) for Cadence.2006a - Dated 28 January, 2008] Authors (including revisions) 1. G. Allan & JL Derome, Version 2.0B 2. JL Derome & F. Liu, Version JL Derome, Version JL Derome, Version 5.0 Approval Authority 1. Dr. Dhamin Al-Khalili, Professor Important: Please read the following disclaimer Information is provided as is without warranty or guarantee of any kind. No attempt has been made to examine this information with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data until you re confident you can implement any of it s procedures in your environment. Copyright 2007, Royal Military College of Canada, Kingston, Ontario. Permission to duplicate and distribute this document is herewith granted for sole educational purpose without any commercial advantage, provided this copyright message is accompanied in all the duplicates distributed, and with prior permission from the Royal Military College of Canada, Department of Electrical and Computer Engineering. All rights reserved. Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA, Synopsys and the Synopsys logo are registered trademarks and Module Compiler is a trademark of Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA

2 Table of Contents Table of Contents... ii List of Figures...i List of Tables... ii 1.0 Introduction Tutorial Description The Basic Design Flow The Design References Conventions Setting up RMC s Environment Tutorial Files UNIX Environment Setup Other UNIX Files of Importance Design Synthesis and Verification Functional Verification of HDL Code Environment Setup for Functional Verification Perform Functional Verification Synthesizing your RTL Code Environment Setup for RTL Synthesis HDL Coding Styles for Synthesis Build the Gate-Level Netlist for the ALU Component Functional Verification on Gate-Level Netlist Environment Setup for Functional Verification Perform Functional Verification on Gate-Level Netlist Insert Scan Chain and Generate Test Pattern Environment Setup for Scan Chain Insertion and Test Pattern Generation Scan Chain Insertion Test Pattern Generation Simulating the Test Patterns Environment Setup for Test Pattern Simulation Perform Functional Verification Adding I/O Cells for DFT Ports Environment Setup for Adding I/O Cells Adding the new Cells Placement, Routing, and Optimization Information on the Layout Section Environment Setup for First Encounter Tool Power Planning Preparing I/Os Importing the Design Key Files and Variables Import Saving the Imported Design Preparing the Floorplan Inserting Core Power Ring and Stripes...17 (ii)

3 4.4.1 Core Power Ring Core Power Stripes Initial Placement and Trial Route for Timing Verification Initial Placement Trial Route for Timing Verification...19 The Slack Browser is not available at RMC for V2006a of Cadence Clock Tree Insertion Golden Netlist Generation and Simulation Generating the Golden Netlist Routing Routing the Power Nets Timing Driven Routing Filler Cells Routing and Timing Verifications Routing Verifications Timing Verifications...23 The Slack Browser is not available at RMC for V2006a of Cadence Exporting Routed Design Layout versus Schematic (LVS) Verification Environment Setup for LVS Verification LVS File Preparation Golden Netlist Preparation DEF File Preparation Importing Design Files into dfii Cadence Environment Importing Verilog Golden Netlist Schematic Preparation for Power Hook Up Importing the DEF file and Layout Preparation Perform LVS DRC Checking Environment Setup for DRC Verification Perform the DRC DRC Setup in CIW Setup Virtuoso for Design Import Run the DRC Verify DRC Output Preparing your Design for Fabrication Environment Setup for DRC Verification Design Name Add Logo Remove the PR Boundary Add Metal and Poly Fill Adding the Fill Perform Final LVS and DRC...35 (iii)

4 List of Figures Figure 1: RMC Basic Digital Design Flow...2 Figure 2: SimVision Design Browser Window...7 Figure 3: SimVision Waveform Window...8 Figure 4: Design Analyzer Window...9 Figure 5: First Encounter Main Window...13 Figure 6: Imported Tutorial Design...16 Figure 7: Specify Floorplan Form...17 Figure 8: Core Area with Power Rings and Stripes...18 Figure 9: Placed Design...19 Figure 11: Small Routed View...21 Figure 10: Power Routing Completed...22 Figure 12: alu_chip Imported Schematic...27 Figure 13: LVS Form...29 Figure 14: LVS Results...29 Figure 15: Logo Placement...33 Figure 16: Final Layout...36 (i)

5 List of Tables Table 1: Conventions used in the RMC Tutorial Documentation...3 (ii)

6 1.0 Introduction 1.1 Tutorial Description This tutorial was written to guide the RMC users through a basic Digital Design Flow Process. The tutorial has evolved from the original CMC s Digital IC Design Flow tutorial at Reference C and is constantly being reviewed and modified to reflect the latest tools and technologies available from CMC. The main purpose of the tutorial is to take a design from a VHDL source file(s) to a RMC ready IC. A RMC ready IC indicates that the student s design has been implemented locally and has passed all the local DRC checks. It is now ready to be submitted through the CMC process if necessary. The RMC design flow tutorial evolved from Reference A into a more complete tutorial (through Design Planner only). The design is fairly simple and requires less effort to run the simulation stages. In addition, some of the descriptions found in Reference B have been included here to give additional explanations on the design process that were not available before. This new version has also been written with the new tools and technology available from CMC. The CMC flow has been updated as well (Reference D) and it has been used to update this tutorial. In essence, this tutorial has been written with the needs of RMC first. This tutorial has been written to work with the following tools and technologies: a. Cadence version 2006a b. Synopsys version 2005a c. Mentor Graphics: i. Calibre version: calibre_2006.2_22.20 ii. DFT version: dft_ d. TSMC: i. CMOSP18 Base: version cmosp18.5.2, and ii. CMOSP18 Artisan: version artisan The Basic Design Flow This tutorial follows a basic HDL design flow. It is not intended to be a complete detailed flow. It is a guide to walk you through a complete flow process. However, it should provide you with enough details for you to understand the basic concepts. The flow being used in this tutorial is depicted in Figure The Design This tutorial is implementing a simple ALU device. It has the following features: a. Asynchronous Clear Signal; b. Data width: 4; c. Registered Output; d. Carry In and Carry Out signals available (active high); e. Clock Enable signal; f. Eight Arithmetic functions implemented: i. S=000: A+B+CI, ii. S=001: A-B-CI, iii. S=010: A+CI, iv. S=011: A-CI, v. S=100: A+1, vi. S=101: A-1, vii. S=110: B+1, viii. S=111: B-1, Introduction (1)

7 Design Synthesis and Verification Placement, Routing and Optimization Layout vs. Schematic Design Rule Checking Prepare For Fabrication { { { { { Main Tasks: a. Functional and Gate Level Simulation b. Synthesis c. DFT Insertion & Pattern Generation d. I/O Cells Insertion e. Create Constraints File Main Tasks: a. Place I/O Cells and Import Design b. Power Planning, and placement c. Clock tree insertion d. Exporting final netlist e. Final routing and verification Main Tasks: a. Import final netlist b. Import final layout c. Design extraction d. Perform LVS Main Tasks: a. Setup DRC Environment b. Perform the DRC c. Verify DRC output Main Tasks: a. Add logo for ID purposes Figure 1: RMC Basic Digital Design Flow Introduction (2)

8 1.4 References A. Tutorial on CMC s Digital IC Design Flow V1.0, Matthew Lewis, Royal Military College of Canada, dated 14 Dec B. Digital Logic Synthesis using the Synopsys and Xilinx - A Tutorial, Ted Obuchowicz, Concordia University, dated July 1998 and revised 3 January C. Tutorial on CMC s Digital IC Design Flow, Canadian Microelectronics Corporation, V1.2 dated 18 December D. Tutorial on CMC s Digital IC Design Flow, Canadian Microelectronics Corporation, V1.0 dated 30 July 2004 (Document ICI-134). E. Meeting between Gord Allan, Carleton University and Jean-Luc Derome, Royal Military College of Canada, October F. Cadence Encounter User Guide, Cadence Product Version 2.3.2, February G. CMOSP18 Design kit, feedx.readme file (CMOSP18 Documentation - Design Pointers: How to Properly Create an I/O Ring (using feeder utility)), dated 31 October H. SOLD V , Volumes 1,2 - (V)HDL Compiler, Guide to HDL Coding Styles for Synthesis 1.5 Conventions Convention Times New Roman Courier Bold Courier Italic Courier Underline Italic Times New Roman Bold Times New Roman Italic Table 1: Conventions used in the RMC Tutorial Documentation Description Regular font used in RMC tutorial documentation Indicates UNIX command syntax. In UNIX command syntax, shows system prompt and command syntax as well as error messages and reports. UNIX Host name. Indicates a form entry required. The user needs to enter fields in the form being displayed to the user. Internet links. We enclose internet link in double quotes as well. File or Directory in the UNIX environment Regular emphasis to bring attention to the reader. It is usually used in the names and cross-references of figures, tables and other paragraphs within the document. It is also used to point to a particular area so that the attention of the reader is focussed on the item desired. \ Indicates the continuation of a command line. / Indicates levels of directory structure. [] Denotes optional parameters, such as pin1 [pin1... pin N]. Indicates a choice among alternatives, such low medium high. This example indicates that you can choose one of the three possibilities listed: low, medium or high. - Connects terms that are read as a single term by the system such as set_annotated_delay. Edit > Copy Indicates a path to a menu command, such as opening the Edit menu and choosing Copy. Indicates a space is required when typing the information on a command line. Introduction (3)

9 2.0 Setting up RMC s Environment 2.1 Tutorial Files The first thing you have to do is to download the demonstration file, tut_artisan.tar, that contains the tutorial information necessary to perform the Design Flow exercise. You can obtain a copy of the compressed tutorial files from the RMC intranet at intranet.rmc.ca/academic/elec/vlsitools/sw/documents/tut_artisan.tar. You will be required to unzip the content of this compressed file by using the UNIX tar command. To help keep your files organized, it is recommended that you keep the design files of a technology in the same directory. Since this tutorial is based on the Artisan technology, it is suggested that you create an artisan directory. To untar the tutorial files, please type the following command at the UNIX prompt (in this example, the tutorial was executed from the cadadm computer): U1=> cadadm$ cd $HOME (ensure that you are in your home directory) U2=> cadadm$ mkdir artisan (only if directory does not exist) U3=> cadadm$ cd artisan U4=> cadadm$ tar xvf tut_artisan.tar The execution of the tar command creates a directory structure that contains the start up files necessary for you to complete the Digital Design Flow tutorial. the directory created is called tut_artisan. 2.2 UNIX Environment Setup The system being used must be configured to run the Cadence, Synopsys, and Mentor Graphics CAD tools. Although the RMC systems should already be setup for these CAD tools, the Cadence System Administrator can be contacted to have your machine setup in this environment if necessary ( request to [email protected]). Now that all the tutorial files have been installed in your home directory, you must setup the licences, path and other necessary UNIX environment elements to run the CAD tools. At RMC, commands have been written to perform this task: gocadence, gosynopsys, godft, and gocalibre. The users must type the commands below at the Unix prompt in order to setup the appropriate environment. U1=> cadadm$. gocadence 2006a U2=> cadadm$. gosynopsys 2005a U3=> cadadm$. godft U4=> cadadm$. gocalibre These commands set up all the directories and licenses needed to run the respective CAD tool. Note that there is a space between the. (dot) and the respective commands. 2.3 Other UNIX Files of Importance There are other files you might want to know about and these are: a. Synopsys uses several setup files in order to function properly. Some of these files can be used effectively to setup your personalized environment or you can work from the default version provided. In this tutorial, we will be working with the following file(s): i..synopsys_dc.setup: This file is use to setup your personalized environment for Design Compiler. This file has been modified to setup the CMC design kits for use with Design Compiler. In particular, all the links and search path for the Artisan 0.18 µm technology are in place for use with the Synopsys tools. ii..synopsys_vss.setup: This file is use to setup the VHDL simulation environment. We do not use this file in this tutorial but it maybe of interest to you in the future. It can exist in three different locations: default system set up, user s home directory, and the current working directory. The Synopsys tool reads the required setup files (if they exist) in the order listed. Each successive reading will override any previous settings found in a previously read file. At a minimum, the default system setup file always exist. The other two can be used to setup a personal configuration or design specific configuration. b. Verilog uses: i. cmosp18_ver.setup c. Cadence uses: i. cds.lib: This is a list of the libraries being used by the designs loaded in the current directory. Additional libraries can Setting up RMC s Environment (4)

10 be added through the Cadence Library Manager. ii..simrc: This is a simulation setup file to indicate what simulation and verification tools is needed. In this tutorial, it is used to setup the LVS environment. d. Mentor uses: i. atpglib: Library build for the CMOSP18 Artisan containing automatic testing devices to insert testability in ASIC designs. Setting up RMC s Environment (5)

11 3.0 Design Synthesis and Verification In this Section, you will build your gate level design from the HDL code of your design. In addition, you will also verify the functionality of your design before and after each important step of the synthesis process to ensure the functionality has not been altered. The following tasks will be performed: a. Functional Verification of the HDL Code (RTL Simulation): Verify the functionality before we build the gate level. This is accomplished with the help of an HDL testbench; b. Synthesizing your RTL Code: Imports the RTL code and creates the gate level netlist (synthesis); c. Functional Verification of the Gate-Level Netlist: Verify the functionality of the gate-level netlist. This is accomplished with the help of an HDL testbench; d. Insert Scan Chain and Generate Test Patterns: It is now time to insert testability in your design. In this tutorial, you will insert a scan chain and generate the appropriate test patterns; e. Simulation of the Test Patterns: Verify that the test patterns work properly; and f. Adding I/O Cells for all Ports: The ALU design is now complete (including the DFT elements). You need to add the I/O cells to create a chip for your component. 3.1 Functional Verification of HDL Code Design Synthesis and Verification In this Section, you ensure that you HDL code meets the functional verification of your project. The tool used to perform this task is NCSIM from Cadence. Please note that your design can be developed with other HDL design entry tools such as Active-HDL or Xilinx Integrated Software Environment (available at RMC). RTL Simulation Environment Setup for Functional Verification In order to perform the functional verification, you need to prepare the UNIX environment. To setup the NCSIM tool, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/simulation/rtl_sim ; and b. Execute the Cadence environment script. gocadence 2006a Perform Functional Verification In order to facilitate your job, a script has been provided to prepare the HDL files and start the simulation tool. To perform the simulation, execute the following tasks: type./scripts in the terminal window. The Design Browser 1 - SimVision window is displayed (shown in Figure 2). Click on the top level icon in the design browser area (shown in Figure 2). The list of signals will be shown in the right window next to the design browser area. Select Select->Signals from the Design Browser 1 - SimVision window. Click on the Waveform icon (circled in Figure 2) in the Design Browser-SimVision window. Waveform 1 - SimVision window is displayed. Type run 4000 ns at the ncsim> prompt of the Console - SimVision window. In the Cadence NC VHDL window, the results of the simulation should be displayed. You should get 27 messages indicating that the test vectors simulated successfully. Again, the waveforms of the selected signals are displayed in the SimVision Waveform 1. You will need to click the view all icon or select View->Zoom->Full X from the SimVision Waveform 1 window. Select File->Exit SimVision from the Waveform 1 - SimVision window. Click Yes in the SimVision Exit window. 3.2 Synthesizing your RTL Code You are now ready to create the gate-level netlist of your design using the Synopsys synthesizer. In order to speed-up the process, this tutorial is using scripts to perform the synthesis. The detailed description of each step is available from Sections 1.2 to 1.5 of Reference D. The major tasks being performed in this Section are: RTL Synthesis Design Synthesis and Verification (6)

12 Waveform Icon Top Level Icon Figure 2: SimVision Design Browser Window a. Importing the RTL code; b. Constraining the design such as clock, output load and I/O directions; and c. Generate the appropriate netlist; Environment Setup for RTL Synthesis In order to perform the RTL synthesis, you need to prepare the UNIX environment. To setup the Synopsys tools, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/synopsys ; and b. Execute the Synopsys environment script gosynopsys 2005a HDL Coding Styles for Synthesis Synopsys provides a guide (Reference H) to describe the structure implied by some HDL constructs and provides coding style examples and techniques HDL designers can apply to their designs. All coding style examples include the timing and area results after synthesis. These results demonstrate that coding style has a direct impact on synthesis quality of results (QOR). This guide can be obtained as follows: Ensure that the synopsys environment is setup as indicated in Section Type sold at the Unix command prompt. The top.pdf window is displayed. Click (V)HDL Compiler in the top.pdf window. The homecore.pdf window is displayed. Click the book to the left of the required guide (Reference H). The toc.pdf window is displayed. This is table of content for the required guide. Design Synthesis and Verification (7)

13 3.2.3 Build the Gate-Level Netlist for the ALU Component The CAD tool used for synthesis is Design Analyzer from Synopsys. In order to execute the script to build the gate-level netlist, execute the following tasks: Type design_analyzer& in the terminal window. The Design Analyzer window is displayed as shown in Figure 4. Select Setup->Command Window... from the Design Analyzer window. The Command window is displayed. The results of the script will be displayed in this window. You are encouraged to open the script in the next task to understand a little better the commands being executed. Select Setup->Execute Script... from the Design Analyzer window. The Execute File window is displayed. Navigate to the cmds directory and select ALU_build.script in the File Name field. Click OK in the Execute File window. The script takes a while to execute. At the end of this script, the files alu_gate.v and alu_gate.vhd are created. These are the gate-level netlists we are looking for. Exit Design Analyzer. 3.3 Functional Verification on Gate-Level Netlist Figure 3: SimVision Waveform Window In this Section, you ensure that you gate-level netlist meets the functional verification of your project. The tools used to perform this task is again NCSIM from Cadence. Gate Level Simulation Design Synthesis and Verification (8)

14 3.3.1 Environment Setup for Functional Verification In order to perform the functional verification, you need to prepare the UNIX environment. To setup the NCSIM tools, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/simulation/gate_sim ; and b. Execute the Cadence environment script gocadence 2006a Perform Functional Verification on Gate-Level Netlist In order to facilitate your job, a script has been provided to prepare the HDL files and start the simulation tool. In order to perform the simulation, perform the following tasks: Execute the command cmds/prep_sim in the terminal window. This makes a local copy of the alu_gate.vhd and a few changes are applied in order for the simulation to work in the NCSIM. The following tasks are performed: - Change all library IEEE for library IEEE, tpz973g, prim (2 Changes to make); - Remove all instances of work. except for work.conv_pack_alu.all (4 changes to make); and - Save the file. Figure 4: Design Analyzer Window Type./scripts_gate_sim in the terminal window. The Design Browser 1 - SimVision window is displayed (shown in Figure 2). Click on the top level icon in the design browser area (shown in Figure 2). The list of signals will be shown in the right window next to the design browser area. Select Select->Signals from the Design Browser 1 - SimVision window. Click on the Waveform icon (circled in Figure 2) in the Design Browser-SimVision window. Waveform 1 - SimVision window is displayed. Type run 4000 ns at the ncsim> prompt of the Console - SimVision window. In the Cadence NC VHDL window, the results of the simulation should be displayed. You should get 27 messages indicating that the test vectors simulated successfully. Again, the waveforms of the selected signals are displayed in the SimVision Waveform 1. You will need to click the view all icon or select View->Zoom->Full X from the SimVision Waveform 1 window. Select File->Exit SimVision from the Waveform 1 - SimVision window. Click Yes in the SimVision Exit window. 3.4 Insert Scan Chain and Generate Test Pattern At this point, you are ready to add testability to your design. In this example we are adding a scan chain using the Mentor Graphics DFT Advisor tool. In addition, this Section will generate test patterns to test the chip for fabrication defects. DFT Insertion Design Synthesis and Verification (9)

15 3.4.1 Environment Setup for Scan Chain Insertion and Test Pattern Generation In order to perform the scan chain insertion, you need to prepare the UNIX environment. To setup the DFT Advisor tool, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/dft ; and b. Execute the Mentor Graphic environment script godft. It is important to note that the dft directory contains a link to a library (atpglib) that contains devices used for building testability in chip. This library has been written for the CMOSP18 Artisan library Scan Chain Insertion In order to facilitate your job, a script has been provided to insert the scan chain for you. However, it is possible to use the tool through a GUI interface. Additional details regarding the use of the GUI interface are provided at Section of Reference D. In order to insert the scan chain, perform the following tasks: Execute the command cp../synopsys/alu_gate.v. in the terminal window. This makes a local copy of the alu_gate.v file. Execute the command dfta.run at the terminal window. The tool reads in the design s netlist and atpglib library, then invokes the DFT Advisor tool. A scan chain is inserted into the design. The file alu_scan.v is created. Other files are also created in the process: dftadvisor.log, alu_scan.dofile and alu_scan.testproc. The last two files are going to be used by DFT Advisor to generate the test patterns Test Pattern Generation Similar to the scan insertion, a script has been provided to generate the test patterns for you. However, it is possible to use the tool through a GUI interface. Additional details regarding the use of the GUI interface are provided at Section of Reference D. In order to generate the test patterns, perform the following tasks: In the dft directory, execute the command fscan.run in the terminal window. Again, the design and library files are read by the fastscan tool. The test vectors are created. The following files are generated: - alu_pattern.v - alu_pattern.v.0.vec - alu_pattern.v.chain1.name - alu_pattern.v.po.name These files will be used to verify the fabricated chip for defects. Vectors and expected results have been generated. In addition, log and working files of the generation have been created: fscan.log, DRC_AU_Faults.txt, alu.ascii and alu.wgl. 3.5 Simulating the Test Patterns In this Section, you verify that the test patterns generated are working properly with the design containing the inserted scan chain. The tool used to perform this task is again NC-Verilog from Cadence Environment Setup for Test Pattern Simulation DFT Verification In order to perform the test pattern simulation, you need to prepare the UNIX environment. To setup the NC-Verilog tool, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/simulation/dft_sim ; and b. Execute the Cadence environment script gocadence 2006a Perform Functional Verification In order to facilitate your job, a script has been provided to perform the simulation. To perform the simulation, execute the following tasks: Design Synthesis and Verification (10)

16 Execute the command cmds/prep_sim in the terminal window. This makes a local copy of the files needed for the simulation (patterns created by the DFT tool). It also makes a local copy of the verilog file created by the DFT software and adds some required definitions for the I/O pads. Those definitions are needed for simulation purposes. type./script_sim in the terminal window. At the end of the simulation, you see a message indicating that no error exist between the simulated results and the expected patterns. 3.6 Adding I/O Cells for DFT Ports The design is almost finish. The remaining tasks are to add the I/O Pad cells for all ALU inputs including the ones generated by the DFT tools. The major tasks being performed in this Section are: a. Adding the ALU wrapper to create the ALU Chip component; b. Importing the ALU chip code (scan chain devices inserted); c. Constraining the design such as output load of the new pins; d. Generating Synopsys constraint files; and e. Generate the final netlist; Adding I/O Cells Environment Setup for Adding I/O Cells In order to add new cells, you need to prepare the UNIX environment. To setup the Synopsys tools, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/synopsys ; and b. Execute the Synopsys environment script gosynopsys 2005a Adding the new Cells The CAD tool used to add the new cells is Design Analyzer from Synopsys. Again, a script has been provided to speed up the process. The details of the task to be performed within Design Analyzer are provided at Section 1.7 of Reference D. In order to execute the script to build the gate-level netlist, execute the following tasks: Execute the command cmds/add_pads in the terminal window. This command adds the wrapper cell to the design and creates the alu_chip component. Type design_analyzer& in the terminal window. The Design Analyzer window is displayed as shown in Figure 4. Select Setup->Command Window... from the Design Analyzer window. The Command window is displayed. The results of the script will be displayed in this window. You are encouraged to open the script in the next tasks to understand a little better the commands being executed. Select Setup->Execute Script... from the Design Analyzer window. The Execute File window is displayed. Navigate to the cmds directory and type add_pads.build in the File Name field. Click OK in the Execute File window. The script takes a while to execute. At the end of this script, the files alu_final.v, alu.sdc and alu.sdf are created. These are the final gate-level netlists files we are looking for. Click the alu_chip icon in the Synopsys Design Analyzer window. Select Analysis->Report... from the Synopsys Design Analyzer window. The Report window is displayed. In the Report window, set the following fields: click Area in the Analysis section, click Power in the Analysis section, click Timing in the Analysis section, click File in the field Send Output To, and enter alu_report.out in the File field. NOTE: Select any other required reports. Click Apply in the Report window. The alu_report.out file is created with the information required. Click Cancel in the Report window. The Report window is closed. Exit Design Analyzer Design Synthesis and Verification (11)

17 4.0 Placement, Routing, and Optimization At this stage, we are starting the physical portion of the design flow. This Section will use the Cadence tool, First Encounter, to create a floorplan and perform the physical layout of your design. You will be performing the following tasks: a. Information required for the layout (I/O and Power); b. Importing Synopsys Design (verilog netlist); c. Preparing the Floorplan; d. Inserting Power Rings and Cores; e. Initial placement and trial route for timing verification; f. Inserting clock tree; g. Golden Netlist Generation; h. Routing and Timing Verifications; and i. Exporting the design for DfII environment. 4.1 Information on the Layout Section All the activities in the Section will use the First Encounter tool and will be executed from the SOC directory. For this tutorial, you are provided with 3 files located in the SOC/inputs directory: a. alu_clk.ctstch: File to be use during the clock tree insertion. It provides the necessary specifications to build the clock tree for your circuit; b. alu.conf: Contains the necessary links to import the design (libraries, placement, etc); and c. alu_placement.io: Placement file for the tutorial. It has all the inputs placed in their proper location; Environment Setup for First Encounter Tool In order to start the First Encounter tool, you need to prepare the UNIX environment. To setup First Encounter, perform the following tasks: U1=> cadadm$ cd tut_artisan/soc U2=> cadadm$. gocadence 2006a U3=> cadadm$ encounter The First Encounter tool will display the main design window shown in Figure 5. In addition, the Encounter prompt encounter 1> is displayed in the shell window. Note that the basic UNIX command such as ls and pwd can be typed at the Encounter prompt Power Planning Power planning is a very important step in your design. Although there are several ways to introduce the power to your design, this tutorial is choosing an early approach to facilitate the floor planning. There are two types of power being provided to your design: Core and Ring. The power pads are provided by library TPZ973g. Several documents are available regarding this library. They are located in directory /CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Documentation/documents/tpz973g_230b. In particular, you can also read the release note document to gain more information on these I/O pads: CMC/kits/artisan/FE/ fe_tsmchome_tpz973g_240c/digital/documentation/release_note/tpz973g_230c.pdf Power Core Layout Preparation The first type of power pad is the core. This is the power that is provided to the core (cells) of your design. The basic idea here is to provide enough pair of power pads (VDD and VSS) for the cells of your design to operate properly. As a rule of thumb, each pair can provide approximately 31 ma of current. At 3.3 V, this is equal to 102 mw of power. At Section 3.6.2, you generated a power report which indicated that the total power consumed by the ALU is mw. Therefore, only one pair of power core pads is needed. For teaching purposes, this tutorial is adding two pairs of core pads. These power pads will be referred to as: a. VDD_CORE0 to VDD_CORE1 and will use core pad PVDD1DGZ; and b. VSS_CORE0 to VSS_CORE1 and will use core pad PVSS1DGZ; Placement, Routing, and Optimization (12)

18 Figure 5: First Encounter Main Window Power Ring The second type of power pad is the ring. This is the power that is provided to the I/Os of your design. This is where the majority of your power is consumed. The basic idea here is to isolate the I/O power from the core to avoid spikes and glitches due to the I/O transitions. The I/O pads being used for this tutorial are the PDIDGZ and PDO08CDG. the power specifications are as follows: a. PDIDGZ: It is a 5V tolerant input pad. It consumes 3.47 uw/mhz. The target frequency of the design is 100 MHz. The ALU is using 17 of the PDIDGZ pads and consumes a total of 5.9 mw; b. PDO08CDG: It is an output pad capable of driving 8 ma and consumes uw/mhz. The target frequency of the design is 100 MHz. The ALU is using 6 of the PDO08CDG pads and consumes a total of 53.4 mw; For this example, we have chosen the PVDD2DGZ to provide the power to the I/O ring. It can provide 22.5 ma to the I/O ring. At 3.3 V, this is equal to mw of power. The total amount of power required for the ALU at 100 MHz is 59.3 mw. Therefore, only one pair of power ring pads is needed. For teaching purposes, this tutorial is adding four (4) pairs of core pads (one for each side). These power pads will be referred to as: a. VDD_RING0 to VDD_RING4 and will use core pad PVDD2DGZ; and b. VSS_RING0 to VSS_RING4 and will use core pad PVSS2DGZ; Placement, Routing, and Optimization (13)

19 4.1.3 Preparing I/Os The next step is to prepare an I/O file to be used during the import process to place the I/Os around the core area of the design. The structure of this file is fairly simple. Each I/O is an entry in the placement file. The format of the line is as follows: a. Pad: I/O Name Orientation Pad_Name ; i. I/O Name: This is the signal name declared in your port declaration; ii. Orientation: This is the side location where you want the input. The possible sides are N (north), S (south), E (east), and W (west); iii. Pad_Name: This is the pad cell selected for this I/O. The different pads are available from library TPZ973g. If the pad name has been identified in the wrapper (as we did), the pad name does not need to be identified again. In our case, only the power and corner pads need to be identified; and b. Example: VDD_RING0 N PVDD2DGZ The placement of the I/Os is dependent on your design. It is best to place the I/Os near the logic in the core where the I/Os are first needed. Normally, the cell placement tool will attempt to do this task. The other factor to take into consideration is to group the I/Os that have a logical association. Remember that this file can be updated and the import redone at any time. Finally, it is recommended that you balance your sides to make the layout easier (equal number of I/O pads on each side). For this tutorial, we have 23 I/O pads from the design and 12 power pads for a total of 35 pads. This is an odd number but we will use additional filler pads (PFEED20) to make it even (2 PFEED20 is equivalent to one I/O pad). Therefore, the design will have 9 pads per side. For this tutorial, the final placement has been done for you and is available as file input/alu_placement.io. You will notice the I/Os are grouped by location (corner, N, S, E, W). It is easier to maintain and update when organized this way Corner Pad Corner pads need to be added to your I/O layout in order to provide the proper power ring continuity in the I/Os. This tutorial needs the following lines in the placement file: a. Pad: BR_CORNER SE PCORNERDG; b. Pad: BL_CORNER SW PCORNERDG; c. Pad: TL_CORNER NW PCORNERDG; and d. Pad: TR_CORNER NE PCORNERDG; Feeders Pads The feeder pads are needed when there are spaces in between the I/O pads. It ensures that the I/O ring is continuous. They are not always required. If the design is I/O driven, it is unlikely that feeder pads are required unless you need them to balance your sides as we did here for the North and South sides. When feeder pads are needed, add a line in between the I/O required. The line entry should be as follows: a. Pad: PFEED20_1 N PFEED20 (as an example). NOTE: The I/O Name must be unique. Therefore, use a naming system with numbers (similar to the VDD and VSS power). In the example shown, one would name the second feeder pad PFEED20_ Bonding Pitch In this tutorial, we did not follow this guideline so that we could keep the size of the die small. However, TSMC is recommending that each pad has a certain width to accommodate the size of the bonding pitch. To accomplish this, you need to add a minimum of 3 PFEED20 feeder cell in between each I/O pad. It is recommended that you incorporate this requirement in your design. Placement, Routing, and Optimization (14)

20 4.2 Importing the Design In this stage, the user will take the synthesize design from Synopsys (Section 3.0), and import it in First Encounter. For your design project, the import step may be iterative (executed more than once) to ensure the design layout is balanced appropriately (the I/O pads). In particular, you need to ensure that enough power pads are provided (I/O ring and core power pads). Therefore, some knowledge of the final structure needs to be prepared ahead of time. Importing Design Key Files and Variables The Design Import form contains many, many features (four different tabs). You do not need all of them but you may in the future. This section discusses the one that are of interest to us for this tutorial. The information is already in the form so you do not have to change anything. The Design tab contains the necessary information for the design to be imported. The inputs for this tab are as follows: a. Verilog Files: This file is generated by the synthesizer and contains the netlist of your design. For the tutorial, this file is../ synopsys/alu_final.v; b. LEF Files: In the Technology Information/Physical Libraries section, the user points the import tool to the technology library. For this tutorial, we only use the LEF files from the Artisan technology from TSMC. The files from the Artisan kit are: i. /CMC/kits/artisan/FE/aci/sc/lef/tsmc18_6lm.lef (standard cell definitions), ii. /CMC/kits/artisan/FE/aci/sc/lef/tsmc18_6lm_antenna.lef (standard cell antenna definitions), iii. /CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Back_End/lef/tpz973g_240a/6lm/lef/tpz973g_6lm.lef iv. (I/O PAD definitions), and /CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Back_End/lef/tpz973g_240a/6lm/lef/antenna_6.lef (I/O PAD antenna definitions). c. Timing Libraries: In the Timing Information section, the user points the import tool to the timing information for the technology. The files from the CMOSP18 kit are: i. /CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Front_End/timing_power/tpz973g_240c/tpz973gwc.tlf (PAD worst case timings), and ii. /CMC/kits/artisan/FE/aci/sc/tlf/slow.tlf (standard cells worst case timings); d. Timing Constraint File: Under the Timing tab, in the Timing Information section, the user points the import tool to the timing information for the design. The constraint file for the tutorial design is: i.../synopsys/alu.sdc; e. Component Name or Footprint: In the Timing Information section, the user needs to identify certain components for delay, buffering and inverting. For this tutorial, these inputs are: i. Buffer name/footprint: BUFX2, ii. Delay name/footprint: BUFX1, and iii. Inverter name/footprint: INVX2; and f. IO Assignment File: In the IO Information section, the user points the tool to a file that contains the required details for the placement of the I/Os around the core. We provided some explanations on how to build such a file in Sections and For this tutorial, the I/O placement file is: i. Inputs/alu_placement.io. We will use the defaults values for the entries in the Core Spec Defaults and Timing tabs of the form. In the Power tab, you will identify the power and ground nets. In the Power/Ground Nets section, enter the following: a. Power Nets: VDD; and b. Ground Nets: VSS Import Now that the placement file has been finalized, you are ready to import the design created in Section 3.0. To instantiate the import form, execute the following steps: Placement, Routing, and Optimization (15)

21 Select Design -> Design Import... in the Encounter Main Window. The Design Import form is displayed. Click on the Load... button in the Design Import window. The Load Import Configuration window is displayed. Navigate to the Inputs directory. Click on the file alu.conf to select it. It should now be highlighted. Click on the Open button in the Load Import Configuration window. The Design Import window should now be loaded with the required information to import your design. Section explains some of the keys files on this form. Click on the OK button in the Design Import window Depending on the design size, it may take a few minutes to load the design. You should now see the design loaded in the Display Area as shown in Figure 6. There are three distinct area in the imported design: - Core: This is the black area with white (or gray) line in the middle. This is where the standard cells will be placed; - IO Ring: Area where your design I/Os have been placed based on the placement file provided; and - Cell listing: At the beginning, the list of standard cells is place in the area to the left of the chip (shown in pink on your screen). Figure 6: Imported Tutorial Design Saving the Imported Design Your design is now imported. It is important to incrementally save your work so that you can return at certain key points in the flow. It is recommended that you save after the design is imported. To save the imported design, perform the following tasks: Select Design->Save Design... in the Encounter Main Window. Navigate to the Saved_Designs directory. Use the directory Saved_Designs in the SOC directory to save your incremental work on the layout. Navigate to the directory. Enter imported.enc in the File name field. Click the Save button. 4.3 Preparing the Floorplan At this time, we are ready to initialize the floorplan. This means that we are determining the shape and size of the core area where the logic cells are going to be placed. It is normally an iterative process (trial and error) until you find the best possible fit for your design. You will notice that for this tutorial, the design is I/O bound. This is cause by the number of I/Os in our Preparing the Floorplan Placement, Routing, and Optimization (16)

22 design and the small logic required to implement the design (the size of the pads are large). One of the factor to take in consideration is that you need to leave enough room for the power ring around the core. To initialize the floorplan, perform the following commands: Select Floorplan -> Specify Floorplan... in the Encounter Main Window The Specify Floorplan window is displayed (shown in Figure 7). In the Specify Floorplan window, set the following fields: Ratio (H/W): 0.4 Core Utilization: 1 Core to Left: 70 Core to Right: 70 Core to Top: 150 Core to Bottom: 150 Leave the remaining field as is. Click the OK button in the Specify Floorplan Window. The core area will be reshaped based on the values above. The new shape should be a rectangle with the long side on the top and bottom. We have reduced the core area to allow the power ring to be added. As mentioned earlier, this step maybe a lot of trial and error to achieve the best possible results. Note that you need to ensure that there is no spaces in between each I/O pad. They must be next to each other so that a complete ring is form on the outside. If the initialization of the floorplan is successful, save the design again as initialized.enc. 4.4 Inserting Core Power Ring and Stripes Figure 7: Specify Floorplan Form At this time, we are ready to prepare the power distribution to the core area. This is accomplished by building a power ring around the core area and adding stripes through the core extending to the ring. Finally, the ring will be connected to the power core pads for external connections to the power supplies. Power Rings and Stripes Placement, Routing, and Optimization (17)

23 4.4.1 Core Power Ring In this tutorial, we will be adding a single ring around the core but keep in mind that as design grows, there may be a need to add more sophisticated power distribution method. The core power ring is composed of actually two rings: VDD and VSS rings. In order to add a core power ring to the tutorial design, perform the following tasks: Select Power->Power Planning->Add Rings... in the Encounter Main Window The Add rings form is displayed. If the other forms were filled out properly, the defaults values here should be fine except for sizes. The width and spacing will be adjusted higher for better power distribution. Change the following inputs: Ensure the Top and Bottom Layers are: Metal5 H Ensure Left and Right Layers are: Metal6 V Change the Top, Bottom, Left and Right Widths: 0.88 Change the Top, Bottom, Left and Right Spacings: 1.38 Change the Top, Bottom, Left and Right Offset: 1.32 Leave all other fields as default Click Ok. You should now see the VSS and VDD power rings around the core area Core Power Stripes The stripes are just another power distribution method. If the core is big, the power near the middle of the core has to travel a long ways to the ring. The stripes are drawn over the core in order to help provide the power farther into the core. Having a great power distribution method is paramount to the success of your design. As a rule of thumb, we add a pair of stripes (VDD and VSS) for every 100 µm of core (in width). For this tutorial, the core area is approximately 132 µm. We will add one pair of power stripes in the middle of the core. To add the stripes to the core, perform the following tasks: Select Power->Power Planning->Add Stripes... in the Encounter Main Window. The Add Stripes window is displayed. Change the following inputs: Ensure Layer is: Metal 6 Width: 0.88 Spacing: 1.38 Click on Number of Sets and enter 3 Click on Relative from core or area X from left: 36 Y from left: 36 Leave all other fields as default Click Ok You should now see the VSS and VDD power stripes added over the core area. Your core area should now look like the one shown in Figure 8. If adding the power rings and stripes is successful, save the design again as powered.enc. Figure 8: Core Area with Power Rings and Stripes NOTE: These stripes are located so that they do not interfere with the power pads feeding the core. We do not want the stripes to align with the core power pads because it will have power routing implication in future steps. Ask the laboratory technician to have a more detailed explanation on the power routing and the placement of power stripes. It is paramount for your project as it will save you time when you have to perform the same task. Placement, Routing, and Optimization (18)

24 4.5 Initial Placement and Trial Route for Timing Verification We are now ready to place the cells into the core area. This task means that the placement tool will take each cell in the netlist and place them in the core area. These cells are usually group by logic meaning that items that are connected together in the netlist will be in close proximity as much as possible. All your timing requirements will be taken into consideration here in order to meet the system clock specified. Placement and Trial Verification Initial Placement To perform the initial placement, execute the following tasks: Select Timing->Report->Clock Waveform... in the Encounter Main Window. The Clock Summary Info window should be displayed. Click Ok in the Clock Summary Info window This task will identify if you have a clock present in your design. Inspect the terminal window where the Encounter tool was started from and look for a clock report. It will contain the period and clock source identification. Select Place-> Standard Cells and Blocks... in the Encounter Main Window The Place window should be displayed. Deselect Reorder Scan Connection. Click Ok in the Place window This task may take a few minutes when designs are large. Select Place-> Check Placement... in the Encounter Main Window The Check Placement window should be displayed. Click Ok in the Check Placement window The placed cells are now shown in the core area as shown in Figure 9 (placement may differ for each user). If the placement is successful, save the design again as placed.enc Trial Route for Timing Verification At this time, you want to perform an initial timing verification before proceeding further. This will help determine if your timing constraints are met. In addition, there are a few steps that can be taken to try to meet the constraints. If these steps are successful, you can avoid making major changes to the design and having to go back and redo some steps (synthesis, floor planning, etc.). To perform the trial route and timing verifications, perform the following tasks: Figure 9: Placed Design Select Route->Trial Route... in the Encounter Main Window The Trial Route window is displayed. The defaults values are OK for trial route. Click Ok in the Trial Route Window Zoom in to observe the routing nets. Select Timing->Extract RC... in the Encounter Main Window The Extract RC window is displayed. Deselect Save Cap to and leave the other fields as default. Click OK in the Extract RC window. Click Timing->Timing Analysis in the Encounter Main Window The Timing Analysis window is displayed. Leave the defaults values in the form. Placement, Routing, and Optimization (19)

25 Click OK in the Timing Analysis window Timing reports are stored in directory SOC/timingReports. In particular, you can browse the directory for.slk file. These files contain the slack timings. For this analysis, look for the alu_chip_prects.slk. Any negative slack indicates that the design does not meet the specifications. The Slack Browser is not available at RMC for V2006a of Cadence Select Timing->Timing Debug->Slack Browser in the Encounter Main Window The Load Timing Slack File window is displayed. Navigate to the file alu_chip_prects.slk located in the tut_artisan/soc directory. Click Open in the Load Timing Slack File window The Timing Slack Browser window is opened and shows the slack report. Ensure that all slack are positive before proceeding to the next step. Click Cancel in the Timing Slack Browser window once you are finished browsing the report There are a few things a designer can try when the timings are not met. This tutorial does not cover these topics but the user is welcomed to try some on his own. Some of these techniques are: a. In-Place Optimization (IPO); b. Synthesis Optimization; c. Interactive ECO; and d. Scan Chain Re-Order. 4.6 Clock Tree Insertion The insertion of the clock tree is a major component of your system. However, these tools make this task look far simpler than it is. The tools needs to insert a balance tree in order to get a perfectly synchronized clock Clock Tree Insertion throughout your circuit. The library should contained the necessary buffers and drivers to build the clock tree. To insert the clock tree, perform the following tasks: From the Encounter prompt, enter specifyclocktree -template This will create a template file, template.ctstch in the directory tut_artisan/soc, for your clock tree insertion. The user needs to modify this file to meet its needs. The clock tree specifications have been provided for this tutorial in file Inputs/alu_clk.ctstch. The user is encouraged to compared the template file against this file to familiarize himself with the clock tree specifications. Select Clock->Specify Clock Tree... in the Encounter Main Window The Specify Clock Tree window is displayed. Click the folder navigation button and navigate to the file Inputs/alu_clk.ctstch. Click Open in the Clock Tree File window Click OK in the Specify Clock Tree window The clock tree specifications are loaded in Encounter. Select Clock->Synthesize Clock Tree... in the Encounter Main Window The Synthesize Clock Tree window is displayed. Change the following inputs: Click on Set Added Clock Buffers as Fixed Leave all other fields as defaults Click OK in the Synthesize Clock Tree window The previous trial route information is cleared. Select Clock->Display->Display Clock Tree... from the Encounter window. The Display Clock Tree window is displayed. Change the following inputs: Leave all other fields as defaults Click OK in the Display Clock Tree window. Again, select Clock->Display->Display Clock Tree... from the Encounter window. The Display Clock Tree window is displayed. Change the following inputs: Click on Display Clock Tree Click on All Level Leave all other fields as defaults Click OK in the Display Clock Tree window. The clock tree is displayed using colors for the added buffers for the clock tree components. Each color indicate a different level for the tree distribution. In addition to the color, a visual connection line (yellow) is displayed to show how the clock is distributed. The user can browse the clock tree using the Clock->Clock Tree Browser... command. It is left to the user to explore this feature. If the clock tree insertion is successful, save the design again as clocked.enc. Placement, Routing, and Optimization (20)

26 4.7 Golden Netlist Generation and Simulation In this step, we are generating the final netlist for the design which will contain all the connections and components. In addition, we could simulate the final netlist against the vectors generated in Section The simulation is not performed in this tutorial as a new test vector needs to be generated. Golden NetList Generating the Golden Netlist The design is essentially complete in terms of components. The scan chain and the clock tree are now present in the design. No other components will be added to the design. Therefore, a final netlist can be created to build the basic schematic for this design (golden netlist). To save the final netlist, execute the following commands: Select Design->Save-> Netlist... in the Encounter Main Window The Save Netlist window is displayed. Change the following inputs: Enter alu_chip_gold.v in the Netlist File: field Leave all other fields as defaults Click OK in the Save Netlist window The golden netlist has been saved in the SOC directory. 4.8 Routing Once the verification of the golden netlist is completed, you are ready to perform the routing. There are two steps to the routing: a. Routing the power nets; and b. Routing the core cells. Routing Routing the Power Nets Routing the power nets consist in connecting the power core pads (VSS and VDD) to the power ring. In the tutorial, we have 4 VDD and 4 VSS pads. Therefore, we should see 8 connections being generated. In addition, the rows are connected to the power ring and stripes. To route the power nets, perform the following tasks: Select Route->Special Route... in the Encounter Main Window The SRoute window is displayed. Leave the fields of the form as defaults. Click OK in the SRoute window The power nets to the pads should now be visible. In addition, the cell row VDD s and VSS s have been extended to their respective rings. There are connected using via arrays. Figure 10 shows the power routing completed. If the power routing is successful, save the design again as srouted.enc Timing Driven Routing One of the last task is to route the remaining nets using the NanoRoute tool. To route the design, execute the following tasks: Select Route->NanoRoute->Route... in the Encounter Main Window The NanoRoute window is displayed. Change the following inputs: In Concurrent Routing Features Area, select Timing Driven, Leave all other fields as defaults Click OK in the NanoRoute window The console or terminal from which Encounter tool was started should come alive. Browse the output for errors. The tutorial is a fairly simple design and should route without any problems. If the routing is successful, no violations should be reported. If you can not see the routing, zoom in the core area (example shown in Figure 11). Once the time driven routing is completed, save the design again as nrouted.enc. Cells Figure 11: Small Routed View Placement, Routing, and Optimization (21)

27 Figure 10: Power Routing Completed 4.9 Filler Cells As you can see in Figure 11, there is a gap between the two cells shown. To complete the layout, you need to fill this gap with filler cells. Execute the following tasks to insert filler cells: Adding Filler Cells Select Place->Filler->Add... in the Encounter Main Window. The Add Filler window is displayed. Click on the Select button. The Select Filler Cells window is displayed. Select all cells in the Cells List area (use the ctl or shift keys for multiple selects) and click the Add button in the Select Filler Cells window. Click Close in the Select Filler Cells window. You should be back in the Add Filler window is displayed. You should see the list of filler cells in the Cell Name(s) field. Enter FILLER in the Prefix field of the Add Filler window and ensure that Fill Boundary is selected. Click OK in the Add Filler window. To see the added filler cells, you need to zoom in the core area. Once the add filler task is completed, save the design again as filled.enc Routing and Timing Verifications In order to be confident that the design can be fabricated, you need to perform a couple of verifications on the design: a. Routing: verification that ensures the design is properly connected (as designed); and b. Timing: verification to verify the design layout is meeting the timing constraints set for this design. Verifications Placement, Routing, and Optimization (22)

28 Routing Verifications You need to perform a high level verification that your connectivity has been completed successfully. This is accomplished with two commands: Verify Connectivity and Verify Geometry Verify Connectivity At this time, you are ready to perform a final connectivity test. This will determine that your routing is completed. To perform this test, perform the following tasks: Select Verify->Connectivity... in the Encounter Main Window The Verify Connectivity window is displayed. Leave all the fields as default. Click OK in the Verify Connectivity window. In the Encounter terminal window, a message indicating that no violations were detected should be displayed Verify Geometry At this time, you are ready to perform a final geometry test. This will determine that your routing meets the layout rules. To perform this test, perform the following tasks: Select Verify->Geometry... in the Encounter Main Window The Verify Geometry window is displayed. Change the following inputs: In Check Area, select Geometry Antenna, Leave all other fields as defaults Click OK in the Verify Geometry window. In the Encounter terminal window, a message indicating that no violations were detected should be displayed Verify Process Antenna At this time, you are ready to perform a final process antenna test. This will determine that your routing meets the antenna rules. To perform this test, perform the following tasks: Select Verify->Process Antenna... in the Encounter Main Window The Verify Process Antenna window is displayed. Change the following inputs: Leave all fields as defaults Click OK in the Verify Process Antenna window. In the Encounter terminal window, a message indicating that no violations were detected should be displayed Timing Verifications At this time, you are to perform a final timing verification. This will determine that you are meeting the timing constraints. To perform the timing verifications, perform the following tasks: Select Timing->Extract RC... in the Encounter Main Window The Extract RC window is displayed. Leave all the fields as default. Click OK in the Extract RC window. Click Timing->Timing Analysis in the Encounter Main Window The Timing Analysis window is displayed. In Design Stage Area, select Post-Route, Leave the defaults values in the form. Click OK in the Timing Analysis window Again, reports are stored in the SOC/reportTimings directory. Search for the file alu_chip_postroute.slk. The Slack Browser is not available at RMC for V2006a of Cadence Select Timing->Timing Debug->Slack Browser in the Encounter Main Window The Load Timing Slack File window is displayed. Navigate to the file alu_chip_postroute.slk located in the tut_artisan/soc directory. Placement, Routing, and Optimization (23)

29 Click Open in the Load Timing Slack File window The Timing Slack Browser window is opened and shows the slack report. Ensure that all slack are positive before proceeding to the next step. In the slack browser window, double click on a row and the net is displayed on the layout. The worst delay is your critical path. Click Cancel in the Timing Slack Browser window once you are finished browsing the report There are additional tools for you to explore (gate count, design browser, etc.). These tools are located under the Tools pull down menu of the Encounter Main window. It will provide additional information on the layout details of the design. It is left to the students to explore Exporting Routed Design The design needs to be exported to the Cadence DFII environment for final preparation. To export the design, perform the following tasks: Type set dbglefdefoutversion 5.5 at the encounter prompt in the terminal window. The terminal window referred to here is the one you launched encounter at Section Select Design->Save->Save DEF... in the Encounter Main Window The Save DEF window is displayed. Keep the form defaults. Click OK in the Save DEF window Exporting DEF Placement, Routing, and Optimization (24)

30 5.0 Layout versus Schematic (LVS) Verification The purpose of this Section is to verify that your physical version (placed and routed) of your design contains the same instances, nets, and connectivity as the verified golden netlist. To accomplish this, you will be performing the following tasks: a. Setup the UNIX environment; b. Prepare files for LVS; c. Importing the files into the dfii environment (verilog golden netlist and DEF); d. Prepare the schematic for power hook up; e. Perform the layout extraction in preparation for LVS; and f. Perform the LVS verification. 5.1 Environment Setup for LVS Verification In order to perform the LVS verification, you need to prepare the UNIX environment. To setup the dfii tool, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/dfii ; and b. Execute the Cadence environment script gocadence 2006a. Environment Setup 5.2 LVS File Preparation Unfortunately, the files created by the previous tools are not quite ready to import in the dfii tool (LVS tool being used at RMC). You will make the necessary adjustments to ensure that the files are properly imported (schematic and layout). LVS File Preparation Golden Netlist Preparation The verilog netlist generated by Encounter does not contain power rails (VDD and VSS). You need to add them before importing the verilog file into the dfii environment. A script was created to perform these changes. Execute the following command: Execute the command Inputs/chg_verilog in the terminal window. This file uses the sed command to make the appropriate changes to the verilog file. Those changes are: 1. add the dummy definitions for I/O pads; 2. add the VSS, VDD pins to the modules (check the different syntax Standard cells vs I/O pads); 3. add the VSS, VDD pins to the alu and alu_chip modules; 4. add the inout statement for the VSS and VDD pins; 5. add the VSS/VDD CORE and VSS/VDD RING pins to the modules; 6. add the inout statement for the VSS/VDD CORE and VSS/VDD RING pins; and 7. add the necessary VDD/VSS Ring and VDD/VSS Core I/O pads. It is recommended to inspect the SED command file to get a better understanding of the changes being made to the verilog file. You will need to create your own for your project DEF File Preparation A message indicating that verilog file alu_chip_dfii.v has been created is displayed. The DEF file generated by Encounter does not contain all via definitions. You need to add them before importing into the dfii environment. A script was created to perform these changes. Execute the following command: Execute the command Inputs/chg_def in the terminal window. This file uses the sed command to make the appropriate changes to the DEF file. Those changes are: 1. Add the VIA definitions necessary for the import into dfii; and 2. Change the number of VIA definitions from 9 to 24 (15 definitions were added). Again, it is recommended to inspect the SED command file to get a better understanding of the changes being made to the DEF file. You will need to create your own for your project. A message indicating that DEF file alu_chip_dfii.def has been created is displayed. Layout versus Schematic (LVS) Verification (25)

31 5.3 Importing Design Files into dfii Cadence Environment Now that the files are ready, we need to import the design files into the dfii Cadence environment to perform the LVS verification. In addition, the schematic needs to be modified to ensure that the power pins are properly hooked up Importing Verilog Golden Netlist As indicated before, the verilog golden netlist contains all the devices to implement the design (including the scan chain and the clock tree elements). We need to verify that the silicon layout created with encounter matches the design schematic. To import the verilog netlist, perform the following tasks: Execute the command cp../samples/.simrc $HOME from the terminal Window. This will ensure that the appropriate environment setup for the LVS tools are present before starting the CIW window. Execute the command startcds -t cmosp18& from the terminal Window. The Cadence ICFB window is displayed. Select File->New->Library... from the ICFB window. The New Library window is displayed. Change the following inputs: In the Library area, enter design in the Name Field, Ensure that the directory listed is the $HOME/artisan/tut_artisan/dfII In the Technology File area, select Attach to an existing techfile, Leave all other fields as defaults Click OK in the New Library window. The Attach Design Library to Technology File window is displayed. Select cmosp18_defin_techlib from the Technology Library pull down selection field in the Attach Design Library to Technology File window. Click OK in the Attach Design Library to Technology File window. The design library is created. Select File->Import->Verilog... from the ICFB window. The Verilog In window is displayed. Using a File Manager window, navigate to the dfii/inputs directory and open Inputs_Verilog_Import file. It contains the necessary entries for the required fields. Change the following inputs: In the Target Library Name field, enter design, In the Reference Libraries field, enter artisan_sc_30 artisan_io_31, In the Verilog Files to Import field, enter alu_chip_dfii.v, In the -v Options field, enter the following two links on the same line: - /CMC/kits/artisan/FE/aci/sc/verilog/tsmc18.v, and - /CMC/kits/artisan/FE/fe_TSMCHOME_tpz973g_240c/digital/Front_End/verilog/tpz973g_240b/tpz973g.v. In the Power Net Name field, enter POWER, In the Ground Net Name field, enter GROUND, Leave all other fields as defaults Click OK in the Verilog In window. This process can take a few minutes depending on the size of your verilog file. A VerilogIn information window is displayed indicating that a log file has been created. Click Yes in the VerilogIn information window. The Log File window is displayed. No errors should be reported. Only messages indicating that the modules of the design are already in the Artisan libraries. Click File->Close Window in the Log File window. A schematic of your design has been created in the design library Schematic Preparation for Power Hook Up In order to prepare the design schematic for proper power hook up, perform the following tasks: Select File->Open... from the icfb window. The Open File window is displayed. Change the following inputs: In the Library Name field, select design, In the Cell Names area, click on alu_chip (Cell Name field should show alu_chip), In the View Name field, select schematic, Leave all other fields as defaults. Click OK in the Open File window. The Virtuoso Schematic Editing window is displayed with the alu_chip design as shown in Figure 12. Select Check->Rules Setup... from the Virtuoso Schematic Editing window. The Setup Schematic Rules Checks window is displayed. Change the following inputs: In the Physical Tab area, select ignored on the Solder on CrossOver field, Leave all other fields as defaults. Click OK in the Setup Schematic Rules Checks window. Layout versus Schematic (LVS) Verification (26)

32 Select Edit->Select->All... from the Virtuoso Schematic Editing window. The Schematic Select All window is displayed. Leave all other fields as defaults. Click OK in the Schematic Select All window. All elements in the schematic window are selected. Select CMC SKILL->Schematic->Hook up pins from the Virtuoso Schematic Editing window. The hookup pins window is displayed. Change the following inputs: Remove all entries except VDDRING, VSSRING, VDDCORE, and VSSCORE, Leave all other fields as defaults. Click OK in the hookup pins window. Ignore the warnings displayed the icfb window. Click the check and save button in the Virtuoso Schematic Editing window. The Schematic Check information window is displayed. You should have 12 warnings and they can also be ignored. Click OK in the Schematic Check window. Select Window->Close from the Virtuoso Schematic Editing window. The Virtuoso Schematic Editing window is closed Importing the DEF file and Layout Preparation Figure 12: alu_chip Imported Schematic Now that the schematic is ready, we need to bring the layout into the design library. To import the DEF file in the design library, perform the following tasks: Select File->Import->DEF... from the ICFB window. The Read DEF File into CellView window is displayed. Using a File Manager window, navigate to the dfii/inputs directory and open the Inputs_Def_Import file. It contains the entries for the Read DEF File into CellView form. Layout versus Schematic (LVS) Verification (27)

33 5.4 Perform LVS Change the following inputs: In the Library Name field, enter design, In the Cell Name field, enter alu_chip, In the View Name field, enter autolayout, Click on the radio button Use, In Ref.Library Names field, enter artisan_sc_30 artisan_io_31. In the DEF File Name field, enter alu_chip_dfii.def, Leave all other fields as defaults Click OK in the Read DEF File into CellView window. It may take a while to import the design depending. In the icfb window, a message indicating that the import is completed should appear (DEFin: completed). Again, ignore the warnings regarding the cell view mode and DEF units. The layout is now imported and it needs a few modifications. Select File->Open... from the icfb window. The Open File window is displayed. Change the following inputs: In the Library Name field, select design, In the Cell Names area, click on alu_chip (Cell Name field should show alu_chip), In the View Name field, select autolayout, Leave all other fields as defaults. Click OK in the Open File window. The Virtuoso layout Editing window is displayed with the uart_chip design. Select Tools->Layout from the Virtuoso layout Editing window. Select Design->Save from the Virtuoso layout Editing window. Select CMC SKILL->P&R->Slot wide metal busses from the Virtuoso Layout Editing window. Select Design->Save from the Virtuoso layout Editing window. The layout is now ready for LVS. You should now be in the Virtuoso layout Editing window. At this time, you are ready to verify the LVS for your design. You need to perform layout extraction and then perform the actual LVS to the extracted version. In order to perform the LVS, execute the following commands: Select Verify->Extract... from the Virtuoso layout Editing window. The Extractor window is displayed. Change the following inputs: Click on the radio button macro cell in the Extract Method, In Rules File field, enter divaext.rul. In Rules Library field, enter cmosp18. Leave all other fields as defaults Click OK in the Extractor window. In the icfb window, you should get no errors. You can ignore the warning regarding the terminals in the autolayout not present in the extracted view. Select Window->Close from the Virtuoso layout Editing window. The autolayout view is closed. Select File->Open... from the icfb window. The Open File window is displayed. Change the following inputs: In the Library Name field, select design, In the Cell Names area, click on alu_chip (Cell Name field should show alu_chip), In the View Name field, select extracted, Leave all other fields as defaults. Click OK in the Open File window. The Virtuoso layout Editing window is displayed with the alu_chip design (extracted view). Select Verify->LVS... from the Virtuoso layout Editing window. The LVS window is displayed. Fill in the form as shown in Figure 13. Click Run in the LVS window. An Analysis Job Succeeded window is displayed. It should indicate that the LVS has succeeded. Click OK in the Analysis Job Succeeded window. Although the job was successful, it does not mean that the LVS has no errors. You need to view the LVS information results. Click the Info button in the LVS window. The Display Run Information window is display. Click on the Log File button on the Display Run Information window. You should see information similar to the one shown in Figure 14. If your results are different than the ones shown in Figure 14, there is a problem with your design. Contact the course staff (lab technician or professor) to help resolve the problem. Layout versus Schematic (LVS) Verification (28)

34 Figure 13: LVS Form The net_lists match. Layout Schematic Instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active total Nets un-matched 0 0 merged 0 0 pruned 0 0 active total Terminals un-matched 0 0 matched but different type 0 0 total 0 29 End comparison: Jan 24 15:24: Comparison program completed successfully. Figure 14: LVS Results Layout versus Schematic (LVS) Verification (29)

35 6.0 DRC Checking The purpose of this Section is to verify that your physical version (placed and routed) of your design meets the foundry s design rule for correct fabrication of your design. To accomplish this, you will be performing the following tasks: a. Setup the UNIX and DRC environments; b. Perform the DRC; and c. Verify DRC output. 6.1 Environment Setup for DRC Verification In order to perform the DRC verification, you need to prepare the UNIX environment. To setup the dfii and DRC tools, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/dfii ; b. Execute the Cadence environment script gocadence 2006a ; and c. Execute the Mentor Graphics DRC environment script gocalibre. 6.2 Perform the DRC You are now ready to perform the DRC on the layout you have just created. The Calibre tool from Mentor Graphics will be used to perform this task DRC Setup in CIW Calibre needs to be setup in the Cadence environment before we can instantiate the tools. In order to setup Calibre in the CIW window, perform the following tasks: Execute the command startcds -t cmosp18 & from the terminal Window. The Cadence icfb window is displayed. Using a File Manager window, navigate to the dfii/inputs directory and open the Calibre_inputs file. It contains the required entries for the Calibre preparation. At the command line of the icfb window, enter the following commands in order listed: load( CMOSP18setupCalibre.il ) load( CMOSP18unsetupCalibre.il ) setuprve() Setup Virtuoso for Design Import At this time, Cadence is ready to interface with the Calibre tool. In this section, you will prepare the tool for DRC verification of the uart_chip. In order to setup Virtuoso for DRC, perform the following tasks: Select File->Open... from the icfb window. The Open File window is displayed. Change the following inputs: In the Library Name field, select design, In the Cell Names area, click on alu_chip (Cell Name field should show alu_chip), In the View Name field, select autolayout, Leave all other fields as defaults. Click OK in the Open File window. The Virtuoso Layout Editing window is displayed with the uart_chip layout. You will notice that a Calibre pull down menu is available now in the menu area. If not, the Calibre setup has not been performed properly. Select Tools->Layout from the Virtuoso layout Editing window. Select Calibre->Setup->Layout Export... from the Virtuoso Layout Editing window. The Calibre Layout Export Setup window is displayed. Change the following inputs: In the Template File field, type /CMC/kits/cmosp18/calibre/template.layout, Leave all other fields as defaults. Click Load in the Calibre Layout Export Setup window. Click OK in the Calibre Layout Export Setup window. Select Design->Save from the Virtuoso layout Editing window. DRC Checking (30)

36 6.2.3 Run the DRC The environment is ready to run the Calibre tool and perform the DRC. In order to run the DRC on the uart_chip, perform the following tasks: Select Calibre->Run DRC from the Virtuoso Layout Editing window. The Calibre Interactive - DRC and the Load Runset File windows are displayed. Click Cancel In the Load Runset File window, select between the following options: - Click Cancel and continue with entering the required data listed below; or - A Runset file calibre_runset is available from the Inputs directory. It contains all the entries listed below. If you use the file, make sure you verify that all the entries listed below are correct. Click the Rules button in the Calibre Interactive - DRC window. The Rules tab of the Calibre Interactive - DRC window is displayed. Change the following inputs: In the Calibre-DRC Rules File field, type /CMC/kits/cmosp18/calibre/RULES_RMC.DRC, Leave all other fields as defaults. Click Load in the Calibre Interactive - DRC window. NOTE: Antenna violations are checked using a different rules file: ANTE.DRC. This is verified by running a separate DRC afterwards if necessary. Click the Inputs button in the Calibre Interactive - DRC window. The Inputs tab of the Calibre Interactive - DRC window is displayed. Change the following inputs: Click the Hierarchical button (diamond shaped), In the Files field, type alu_chip.calibre.gds, In the Top Cell field, type alu_chip, Leave all other fields as defaults. Click the Outputs button in the Calibre Interactive - DRC window. The Outputs tab of the Calibre Interactive - DRC window is displayed. Change the following inputs: In the DRC Results Database field, type alu_chip.ascii, Click ASCII in the format field, Click Show results in RVE, Click Write DRC Summary Report File, In the File field (bottom area of tab), type alu_chip_drc.summary, Leave all other fields as defaults. Click the Run DRC button in the Calibre Interactive - DRC window. The Calibre - DRC RVE and DRC Summary Report windows are displayed. NOTE: In the Calibre tool, they use a coloring scheme in the fields. If your entry turns green, it indicates that the tool is recognizing your entry properly. Black and Red are usually used to indicate the need to enter a value (some exceptions to this rule exist). 6.3 Verify DRC Output The DRC Summary Report gives a text summary of the DRC run while the Calibre-DRC viewer allows the DRC errors in the design to be browsed through graphically. At this time, the DRC is complete. If you have errors, they need to be addressed before finalizing the design for fabrication. Consult the ECE staff for help on how to correct the DRC errors. In reference Reference D, there are a few instructions on how to navigate the errors within the RVE interface. In this tutorial, you will find density errors relating to each metal level and poly. These errors will be handled in the Section 7.0. It is to note that after adding these layers, another LVS and DRC must be performed to ensure nothing in the design has been changed. DRC Checking (31)

37 7.0 Preparing your Design for Fabrication The final step to the design flow is to add a label to uniquely identify your design for CMC. In addition, you will ensure that design meets the fabrication requirements. This section will guide you into this process. To accomplish this, you will be performing the following tasks: a. Add a design logo for identification purposes; b. Add metal and poly fill; and c. Run final LVS and DRC. 7.1 Environment Setup for DRC Verification In order to add a logo to your design, you need to prepare the UNIX environment. To setup the dfii tools, perform the following tasks: a. Open a terminal window and navigate to the directory tut_artisan/dfii ; and b. Execute the Cadence environment script gocadence. 7.2 Design Name A CMC design name has the format TTUUXXX where TT is the technology two-letter code, UU is your university's two letter code and XXX is a name you choose for your design (it must be unique within your university - make sure of this!). An example is CDRMABC which indicates a design in the CMOSP35 technology from the Royal military College of Canada with a user-selected name of ABC. In normal circumstances, you would submit your design to CMC to perform a DRC and for fabrication. When you submit a design by FTP to CMC as a design file, you must prefix a "D" or an "I" to the design name for DRC or Implementation, respectively. So in this example, DCDRMABC is the name of the design file submitted to CMC for DRC and ICDRMABC is the name of the design file submitted to CMC for fabrication. We will NOT perform these tasks for the tutorial. 7.3 Add Logo In order to uniquely identify your tutorial design, you must assign a logo that will be placed somewhere on your design. Normally, this identifier would have been assigned to you by CMC (at least for the tutorial at Reference D). For demonstration purposes, our tutorial design name will be CFRMTUC. CF identifies the design as a CMOSP18 design. RM is the RMC university code and TUC indicates the Tutorial Uart_Chip. Should you want, you can assign your own design name for the tutorial (change only TUC). For instruction purposes, the rest of these instructions will assume a logo of CFRMTUC. Although the full code is CFRMTUC, only the last five letters will be used to form the logo on the die: RMTUC. In addition, make sure the Logo Layer has been selected as top metal. For example, metal3 for CMOSP35 and metal6 for CMOSP18. Execute the following to add a logo: Execute the command startcds -t cmosp18 from the terminal Window. The Cadence icfb window is displayed. Select File->Open... from the icfb window. The Open File window is displayed. In the Open File window, set the following fields: Library Name: design (pull down menu) Cell Name: alu_chip View Name: autolayout (pull down menu) Click OK in the Open File window Virtuoso Layout Editing and LSW windows are displayed. Select CMC Gateway->Place Logo in the icfb window Create Logo Instance Form window is displayed. In the Create Logo Instance Form window, set the following fields: Logo String: RMTUC (or your assigned code) Logo Layer: metal6, dg Logo Magnification: 0.5, Logo Spacing: 2.0 NOTE: The size of the logo may need to be adjusted for your own design to ensure it fits inside your design. Contact the ECE staff to learn how. Also note that if a logo was created previously, its layout needs to be removed to create a new one. Click OK in the Create Logo Instance Form window At the command line of the Virtuoso Layout Editing window, you will be prompted to "Enter the Logo cell Lower Left origin...". In the Virtuoso Layout Editing window, point the mouse locator ABOVE the die and left-click your mouse to place the logo at that location (well out of your design area). Preparing your Design for Fabrication (32)

38 Select all the letters of the logo using your left mouse. Click on the Move icon in the Virtuoso Layout Editing window Move window is displayed. In the Move window, set the following fields: Snap Mode: anyangle (pull down menu). Click Hide in the Move window. Click once on the selected logo. The logo is now selected and can be moved anywhere in the design (it follows your mouse). Left click once to drop the logo on the lower left corner of the core area and ensure it does not interfere with other layers (metal 6 in particular). Figure 15 shows where the logo should be positioned. Note: You should now zoom-in on the logo to double check to ensure you have not shorted any traces. Click the Save button. Figure 15: Logo Placement 7.4 Remove the PR Boundary There is a prboundry layer which will cause problems for the automated fill routine if it is not removed. Press "f" in the Virtuoso Layout Editing window. This command will fit the design to the screen. Click on prbound by in the LSW window. prbound By should be selected. Preparing your Design for Fabrication (33)

39 Click on NV and NS in the LSW window Right-click on prbound by in the LSW window. This command will make that layer selectable. Left-Click inside the Virtuoso Layout Editing window. Press Ctl-R in the Virtuoso Layout Editing window. This command will redraw the screen with the appropriate layers visible. Point the mouse in the Virtuoso Layout Editing window You should see a dotted line around the edge of your design. If it is not present, ignore the delete command and execute the save command. Left-Click in the Virtuoso Layout Editing window. The edge of your design should turn white. Select count should indicate 1 (top row of the Virtuoso Layout Editing window). You have just selected the design Place & route boundary. NOTE: Ensure that only the outside boundary is selected and not and I/O pad boundary before performing the next command. It is alu_chip boundary that we are targeting. Select Edit->Delete in the Virtuoso Layout Editing window. The design Place & route boundary will be deleted. Save your design one last time. Select Design->Save in the Virtuoso Layout Editing window. You can make the layers visible again by clicking AV in the LSW window and Ctl-R in the Virtuoso Layout Editing window. Your design will look exactly the same after deleting this PR boundary, but some skill routines needed for submission to CMC will work with this boundary remove. 7.5 Add Metal and Poly Fill Technology suppliers have minimum metal and poly density limits for designs. You will need to add fill to your design to meet those requirements. The required fill minimums and your current fill percentages are available from your CMC DRC results page. Adding metal fill to your layout makes it very difficult to view or make any additional edits to your design. Because of this, for your own design you may want to save your layout again (under another name) before adding fill. Since this tutorial example design is not being fabricated and to avoid unneccessary disk usage, you do not need to make the extra save. If your final DRC still has problems not related to the fill, you will find it much easier to fix those problems on the pre-filled version of the layout, and then run the fill routine again than to try and fix the filled version of your design Adding the Fill You should already have the Cadence application running at this time. To add the poly and metal fills, execute the following tasks: Select File->Open... from the icfb window. The Open File window is displayed. In the Open File window, set the following fields: Library Name: design (pull down menu) Cell Name: alu_chip View Name: autolayout (pull down menu) Click OK in the Open File window Virtuoso Layout Editing and LSW windows are displayed. Select Tools->Layout from the Virtuso Layout Editing window. If the layout does not display, click the maximize button on the top right corner. Select Create->Instance from the Virtuso Layout Editing window. The Create Instance window is displayed. In the Create Instance window, set the following fields: Library field: cmosp18 Cell field: dummyfill View field: layout In Mosaic area, set the following field: Rows: Columns: You can also use the browse button to select the component (left to the reader to explore). In addition, if you are creating the dummyfill array on your own design, you will have to experiment with Rows and Columns values until you find one that is close. Or you can calculate the required size based on the area you wish to cover and the 4 by 7 micron size of the basic fill cell. Click Hide in the Create Instance window The outline of the component should be visible in the layout area when your mouse is moved over your design. Position the outline in the middle of the core and click once in the Virtuso Layout Editing window. The new instance should fit just inside the I/O ring. Click Hide in the Virtuso Layout Editing window. This will disable the create instance command. Select Verify->DRC from the Virtuso Layout Editing window. The DRC window is displayed. Preparing your Design for Fabrication (34)

40 In the DRC window, set the following fields: Rules field: divafill.rul Rules Library: cmosp18 Click the Set Switches and select all switches available (use the shift key for multiple selections) Leave the default value for the other fields Click OK in the DRC window Diva will now fill the region you selected by placing the dummyfill instance with a valid fill pattern, then cut-back the fill pattern wherever it interferes with existing metal (poly) of that same layer. To view the added layers, you need to zoom in close. In addition, you need to restrict the number of layers that are visible to avoid the confusing and busy look. Select Design->Save from the Virtuso Layout Editing window. Your final design is now saved. 7.6 Perform Final LVS and DRC Ensure edits have not introduced new errors by running the verification tasks LVS and DRC on the new layout with the logo and the fillers (metals and poly). When you try and run the LVS you may get a note saying the run directory differs from the form contents. Change the Run Directory to LVS2 (or some other unused directory name). Any LVS errors that appear now are the result of your edits, and any DRC problems remaining were either missed, or created with your edits. You will need to repeat the edit, LVS & DRC process on this layout until you have no errors. Both LVS and DRC should be 100% "clean" at this point. Your final design should look like the one shown in Figure 16. It is shown in black and white for printability (most people only have access to a B&W printer). Please note that some of the DRC Rules have been relaxed for this tutorial (density rules). This is due to the size of the design where those rules could not be met. Now the design is ready for the initial submission to CMC s DRC service. You have now completed the RMC Design Flow Tutorial.. Preparing your Design for Fabrication (35)

41 Figure 16: Final Layout Preparing your Design for Fabrication (36)