Seeking Opportunities for Hardware Acceleration in Big Data Analytics

Transcription

1 Seeking Opportunities for Hardware Acceleration in Big Data Analytics Paul Chow High-Performance Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Toronto

2 Who am I? I am interested in building computing machines/accelerators Why accelerate? To go faster, to reduce power How to accelerate? 2 We use FPGAs What are we doing? Some of our projects What are the opportunities in Big Data?

3 Moore s Law 3

4 Until 4 I m melting!!!! - Wizard of Oz 1939

5 More cores!!! 5 Programming hard and it s not always fast enough

6 Need for accelerators GPUs 6 FPGAs

7 What about these FPGAs? First, a quick introduction. 7

8 FIELD-PROGRAMMABLE GATE ARRAYS 8

9 FIELD-PROGRAMMABLE GATE ARRAYS 9 H.Roesner flickr / MadPhysicist

10 Hardwired FPGA functions SRAM Ser Des ARM A9 ARM A9 DSP 1 0 SRAM 1GE MAC

11 Computing with FPGAs Fully customized dataflow and buffering Tightly coupled pipelining of computations Very low energy / computation ratio 1 1

12 Example: Smith-Waterman DNA sequencing (Dynamic Programming) 49x 980x speedup (I/O dependent) on Xilinx V4-LX160 FPGA vs GHz AMD Opteron (Storaasli/Cray 2009)

13 Molecular Dynamics Simulate motion of molecules at atomic level Highly compute-intensive Understand protein folding Computer-aided drug design 1 3

14 Platform for MD Initial Breakdown of CPU Time 12 short range nonbond FPGAs 2-3 pipelines/nbe FPGA; Each runs 15-30x CPU NBE x 2 PME FPGAs with fast memory and fibre optic interconnects PME 420x Short range Nonbonded Long range Electrostatic Bonds Bonds on quad-core Xeon server Bonds 1x MEM PME 72.5 GB/s 1 PME MEM 4 NBE NBE NBE NBE NBE NBE Sys Mem Sys Mem NBE NBE NBE NBE NBE NBE Sys Mem FSB FSB FSB Quad Socket Xeon 0 Socket 1 Socket FSB MHz Socket 3

15 Performance Significant overlap between all force calculations ms is equivalent to between 80 and 88 Infinibandconnected cores at U of T s supercomputer, SciNet hyperthreaded cores Can we do better? 140 with hardware bond engines change engine from SW to HW, no architectural change

16 ISCA 2014 June 16, 2014 More Recently A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services Demonstrates that FPGAs can work in a data centre Accelerate the Bing ranking engine Double performance for only 10% increase in power To be deployed in Bing in 2015! 1 6

17 Traditional Programming of an FPGA 1 7

18 Design Flow Design conception DESIGN ENTRY Schematic capture Verilog Synthesis Functional simulation No Design correct? Yes Physical design 1 8 Timing simulation No Timing requirements met? Chip configuration Figure A typical CAD system. Brown and Vranesic, Fundamentals of Digital Logic Design with Verilog, 2 nd ed.

19 Placement 1 9 Figure Placement of the circuit in Figure Brown and Vranesic, Fundamentals of Digital Logic Design with Verilog, 2 nd ed.

20 Routing 2 0 Figure Routing for the placement in Figure Brown and Vranesic, Fundamentals of Digital Logic Design with Verilog, 2 nd ed.

21 Timing 2 1 Table A summary of static timing analysis results. Brown and Vranesic, Fundamentals of Digital Logic Design with Verilog, 2 nd ed.

22 FPGA Programmability Drawbacks Need to understand hardware design Implementation (compile-equivalent) takes hours Established Hardware Description Languages (Verilog HDL, VHDL) are very low-level Downside of design flexibility: No established programming models 2 2

23 Programmability is Improving Higher-level HDLs SystemC, SystemVerilog, Bluespec High-Level-Synthesis ( C-to-gates ) Very active area in research and industry, but: So far, only useful if programmer understands hardware Target not just an instruction set designing the processor too! Higher level of abstraction allows easier design exploration Today, possible to achieve better than hand design in some cases 2 3

24 So, why are FPGAs still interesting? Even at 10% of a CPU/GPU clock rate Very high performance for the right applications Building an application-specific computer Custom memory architectures Data stream processing especially fits Caches don t get in the way Fine-grain parallelism Bit manipulation Pattern matching Performance per watt 25W per chip versus 150W per chip Compute density Racks of servers reduced to less than one 2 4

25 Often used closer to the data 2 5

26 2 6 SOME POSSIBLY RELEVANT PROJECTS

27 FPGAs as OpenStack Cloud Resources VFR... FPGA(s) VFR Agent VM... VM Agent Hypervisor 2 7 Server Server OpenStack Control & Management (C & M) Now we can boot a network connected FPGA accelerator on demand, in seconds! Framework for HLS use HLS to create and then drop in accelerators

28 Outside World Data Center Example VM Resource VFR Site Requests Uploads Web Server Internal Network Data analysis engine 2 8 x Dynamically scalable according to demand Same OpenStack command to boot/release either resource!

29 Accelerators under Hadoop A Hadoop cluster with one x86 as master node and eight ZedBoards as slave nodes FPGA: computation ARM processor: communication and task tracing 2 9

30 MapReduce Data Flow HDFS Data0 Data1 Data2 Map Map Map 3 0 Reduce HDFS Result

31 MapReduce Data Flow HDFS Data0 Data1 Data2 Map Map Map 3 1 Reduce HDFS Result

32 MapReduce Data Flow with FPGA HDFS Data0 Data1 Data2 FPGA Map FPGA Map FPGA Map 3 2 Reduce HDFS Result

33 PGAS: Global Shared Memory Host CPU (x86) DRAM DRAM Application SRAM Embedded CPU Application FPGA SRAM Custom Hardware Soft API Network Drivers Soft API Hard API Hard API 3 3 Network Easy data transfers between all system memories Productive but efficient high-level programming model

34 HPC system: BEE4 + PC hosts PCIe 2 x8 3.2 GB/s 2x 16GB DDR Gb Eth

35 Low power, embedded system: Zynq DRAM FPGA 1Gbit Ethernet CH Gc BlockRAM x8 3 5 BlockRAM CH Gc On-Chip Network CH Gc BlockRAM

36 Big Data Memory Systems 3 6 To explore the use of FPGAs in the architecture of Big Data memory Tools systems to Tackle Big Data

37 Are there better memory architectures? 3 7 Replace middleware in-memory system with application-specific Tools to Tackle architecture Big Data

38 We Need Applications! We are not users We do not understand the applications Do you have a potential application? We could collaborate 3 8 pc@eecg.toronto.edu

39 Conclusions FPGAs are handicapped by the tools hard to use Good Abstraction is being raised Bad Iteration time is very long can be hours FPGAs can provide better performance for many interesting applications 3 9 FPGAs can provide better performance per watt There should be good opportunities for FPGAs in Big Data what are they?

40 Thank you for your attention! Questions? 4 0 Paul Chow pc@eecg.toronto.edu