Introduction to CMOS VLSI Design

Transcription

1 Introduction to CMOS VLSI esign Slides adapted from: N. Weste,. Harris, CMOS VLSI esign, Addison-Wesley, 3/e, 24 Introduction Integrated Circuits: many transistors on one chip Very Large Scale Integration (VLSI): very many transistors on one chip Complementary Metal Oxide Semiconductor (CMOS): fast, cheap, low power 2

2 Outline A Brief History MOS transistors CMOS Logic CMOS Fabrication and Layout Chip esign Challenges System esign Logic esign Physical esign esign Verification Fabrication, Packaging and Testing 3 A Brief History T-R-A-N-S-I-S-T-O-R = TRANsfer resistor 947: John Bardeen, Walter Brattain and William Schokley at Bell laboratories built the first working point contact transistor (Nobel Prize in Physics in 956) 958: Jack Kylby built the first integrated circuit flip flop at Texas Instruments (Nobel Prize in Physics in 2) 925: Julius Lilienfield patents the original idea of field effect transistors 935: Oskar Heil patents the first MOSFET 963: Frank Wanlass at Fairchild describes the first CMOS logic gate (nmos and pmos) 97: Processes using nmos became dominant 98: Power consumption become a major issue. CMOS process are widely adopted. 4

3 A Brief History Integrated Circuits enabled today s way of life 8 transistors manufactured in 23 million for every human on the planet 5 Moore s Law In 963 Gordon Moore predicted that as a result of continuous miniaturization transistor count would double every 8 months 53% compound annual growth rate over 45 years No other technology has grown so fast so long Transistors become smaller, faster, consume less power, and are cheaper to manufacture 6

4 Clock Frequencies of Intel Processors Transistor count is not the only factor that has grown exponentially, e.g. clock frequencies have doubled roughly every 34 months 7 Chip Integration Level SSI = small-scale integration ( up to gates) MSI = medium-scale integration ( up to gates) LSI = large-scale integration (up to gates) VLSI = very large-scale integration (over gates) 8

5 Technology Scaling 97: Intel 44 transistors with minimum dimension of um 23: Pentium 4 transistors with minimum dimension of 3 nm Scaling cannot go on forever because transistors cannot be smaller than atoms 9 The Productivity Gap esigners rely increasingly on design automation software tools: to seek productivity gains to cope with increased complexity Source: SEMATECH

6 licon Lattice licon is a semiconductor Transistors are built on a silicon substrate licon is a Group IV material Forms crystal lattice with bonds to four neighbors opants Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) As B - 2

7 Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nmos and pmos MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration 3 MOS Transistors Four terminals: gate, source, drain, body (= bulk = substrate) 4

8 nmos Operation Body is commonly tied to ground ( V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate rain Polysilicon O 2 n+ p n+ bulk S 5 nmos Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body channel under gate gets inverted to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate rain Polysilicon O 2 n+ p n+ bulk S 6

9 pmos Transistor milar, but doping and voltages reversed Body tied to high voltage (V ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Polysilicon Source Gate rain O 2 p+ p+ n bulk 7 Power Supply Voltage GN = V In 98 s, V = 5V V has decreased in modern processes High V would damage modern tiny transistors Lower V saves power V = 3.3, 2.5,.8,.5,.2,., 8

10 MOS Transistors as switches We can model MOS transistors as controlled switches Voltage at gate controls path from source to drain 9 CMOS Technology CMOS technology uses both nmos and pmos transistors. The transistors are arranged in a structure formed by two complementary networks Pull-up network is complement of pull-down Parallel -> series, series -> parallel 2

11 CMOS Logic Inverter A ON OFF = = = = OFF ON Y 2 CMOS Logic NAN 22

12 CMOS Logic NOR 23 CMOS Logic Gates (a.k.a. Static CMOS) Pull-up network is complement of pull-down Parallel series, series parallel 24

13 Compound Gates Example: Y = (A+B+C) ABC Y 25 Compound Gates 26

14 How good is the output signal? gnal Strength Strength of signal How close it approximates ideal voltage source V and GN rails are strongest and sources nmos and pmos are not ideal switches nmos pass strong, but degraded or weak pmos pass strong, but degraded or weak Thus: nmos are best for pull-down network pmos are best for pull-up network 27 Pass Transistors Transistors can be used as switches 28

15 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both and well 29 Static CMOS gates are fully restored In static CMOS, the nmos transistors only need to pass s and the pmos only pass s, so the output is always strongly driven and the levels are never degraded This is called a fully restored logic gate 3

16 Static CMOS is inherently inverting CMOS single stage gates must be inverting To build non inverting functions we need multiple stages 3 Tristates Tristate buffer produces Z when not enabled EN A Y Z Z 32

17 Nonrestoring Tristates Transmission gate acts as tristate buffer Only two transistors But nonrestoring A is passed on to Y as it is (thus, Y is not always a strong s or s) 33 Tristate Inverter Tristate inverter produces restored output For a non inverting tristate add an inverter in front 34

18 Multiplexers 2: multiplexer chooses between two inputs S X X X X Y S Y 35 Gate-Level Mux esign Y = S + S How many transistors are needed? S Y = 2 = = Too Many!! S Y 36

19 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors 37 Inverting Mux Inverting multiplexer Use compound gate or pair of tristate inverters Essentially the same thing For noninverting multiplexer add an inverter 38

20 Latch When =, latch is transparent flows through to like a buffer When =, the latch is opaque holds its old value independent of a.k.a. transparent latch or level-sensitive latch Latch 39 Latch esign Multiplexer chooses or hold 4

21 Latch Operation = = 4 Flip-flop When rises, is copied to At all other times, holds its value a.k.a. positive edge-triggered flip-flop, masterslave flip-flop Flop 42

22 Flip-flop esign Built from master and slave latches M Latch M Latch 43 Flip-flop Operation M = M = 44

23 Summary If the automobile had followed the same development cycle as the computer, a Rolls Royce would today cost $, get one million miles per gallon, and explode once a year Robert X. Cringely, InfoWorld Magazine 45