All Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule

Transcription

1 All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems

2 Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries Research: Education: 2.8 Mio. CHF 1.9 Mio. CHF 2

3 Contents Sequential vs. Parallel Data Processing Properties and Architectures of SoC FPGA Comparing Competitors Second Generation SoC FPGA 3

4 Microcontroller with Cortex M4 Source: ST Micro STM32F3 4

5 Parallel Processing Finite Impulse Response Filter Ethernet Switching & Routing Source: Altera DSP Users Guide 5

6 Synchronous Parallel Logic 6

7 Classic FPGA FPGA Fabric Interconnection between Logic Cells Logic Cell Lookup Table Image courtesy of Clieve Maxfield 7

8 FPGA with Hard Silicon Blocks Logic Element Block RAM Multiplier DSP block PLL Clock Manager I/O Bank Transceiver 8

9 Example of DSP Hard Block FIR Filter Register Filter coefficient Accumulator Digital Signal Processing Slice Source: Altera DSP Users Guide Scalable Multiplier Accumulator Konfig. Altera Cyclone Xilinx Zync 1 9x9 25x x19 35x x27 42x18 Source: Xilinx Users Guide 9

10 Parallel and Sequential circuits coexist Source: Altera 10

11 System Level Benefits of SoC Increased system performance 4,000 DMIPS for under 1.8W Up to 1,600 GMACS, 300 GFLOPS DSP >125 Gbps processor to FPGA interconnect Cache coherent hardware accelerators Reduced power consumption Estimated up to 30% power savings vs. 2-chip solution Reduced board size Up to 55% form factor reduction As few as two power rails Reduced system costs Lower component cost Reduction in PCB complexity and cost Less routing with fewer layers Source: Altera 11

12 SoC FPGA & Silicon Convergence Classic FPGA General Processor ASIC ASSP SOC FPGA + Great flexibility - No Hard Processors - Licensing costs for IP + Software programmable + Great flexibility - Few application specific features + Customer Specific + Great power efficiency - High development costs - High turnaround times - Poor flexibility + Power efficient + No licenses + Great power efficiency -Poor flexibility + Good power efficiency + Less board space + High interconnect speed 12

13 SoC FPGA Architecture Dedicated MPU Pins UART CAN I2C SPI SD/SDIO GPIO Timer GigEth USB OTG Static Memory Controller DMA Interconnect ARM Cortex-A9 Neon/FPU L1 Cache Debug and Trace Block Memory L2 Cache 100 Gbps Bridges FPGA Fabric ARM Cortex-A9 Neon/FPU L1 Cache Multiport DDR2/3 Controller DSP Blocks Dedicated DDR Pins 1) Only Altera 2) Only Xilinx Scratch SRAM Boot ROM Multiport DDR2/3 Controller 1) PCIe A/D Conv. 2) FPGA Pins Transceivers 13

14 SoC Processor Cores Altera Xilinx CPU-Core Dual ARM Cortex-A9 MPCore Dual ARM Cortex-A9 MPCore Debug CoreSight CoreSight Neon-SIMD Neon-SIMD CPU Clock frequency 1) MHz MHz L1-Cache (Data/Instruction) 32 KB/ 32KB parity protected 32 KB/ 32KB parity protected L2-Cache 512KB ECC protected 512KB no ECC parity protected Scratch SRAM 64KB ECC protected 256KB parity protected Boot ROM 64KB 128 KB 1) CPU Clock frequency depends on speed grade 14

15 Comparing Altera and Xilinx Mid End Altera Arria V5ASTD3 Xilinx Zync Z-7045 Package Variants 3 3 FPGA I/O Pins FPGA Logik 350k Logikelemente 350k Logikzellen FPGA Block-RAM 17.2 Mbit 17.4 Mbit Serial Transceivers 1) 30 x Gbits/s 16 x 12.5 Gbps or 16 x 10.3 Gbit/s SDRAM Controller 32-bit DDR2/DDR bit DDR2/DDR DSP Slices 1618 (18x19 config.) x25 (config.) DSP Performance 1197 GMAC/s 1334 GMAC/s A/D Converters none 2 x 12 bit MSPS 17 inputs Static Power/W Total Power/W ) For largest package 15

16 Altera QSYS System Konfigurator 16

17 Operating Systems available for Altera SoC 17

18 2 nd Generation SoC FPGA What has the 2 nd Generation to offer? 18

19 Intended Altera 2nd Generation 1. Generation Altera Arria 5 2. Generation Largest Altera (Arria 10) Process 28nm 20 nm Low Power Prozessor Clock 800 MHz 1.5 GHz (overdrive) Logic Elements 504k 1150k Power Dissipation 1x 0.6x Max Transceivers speed Gbps Gbps Memory Devices DDR3 SDRAM 1333Mbps DDR3 SDRAM 2133Mbps DDR4 SDRAM 2666 Mbps Soc SRAM 64KB 256kKB FPGA-MPU Bridge Up to 64-bit Up to 128-bit Code Encryption - Secure Boot DSP Blocks 27 x 27 Multipliers 54 x 54 Multipliers 19

20 Questions 20