Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
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1 Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm Computer Technology /99
2 Overview Ultra-Low-Power Electronics Reconfigurable Modules Structure TR-FSM Design of Reconfigurable Modules Interconnect Generation Interconnect Topology Optimization Algorithm Evaluation Results Full Design Flow Summary Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 2/19
3 Ultra-Low-Power Electronics Application: WSN Node in a SoC CPU as Master Sleep, Wakeup Offload-Engines Multiple Modules Reconfigurable Various Applications Adapt to Environment WSN Node CPU Mem RTC SoC SoC Comm. RF Intf. GPIO Sensor Interface ADC RF GPIO ADC Sensor Sensor Power Power Mgmt. Mgmt. Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 3/19
4 Reconfigurable Logic Development Pre-Silicon vs. Post-Silicon Fine-Grain vs. Coarse-Grain Heterogeneous Domain Specific Application Class Pre-Silicon Post-Silicon Reconfigurable Circuit Manufacturing Application 1 Application n Bitstream Bitstream Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 4/19
5 Structure Interface FSM+D Control, Data, Arithmetic Cell Types FSM Memory Add, Subtract, A-B,... Reconfigurable Routing Cells Bus Intr Clk Reset Config Param FSM A-B P > I/O Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 5/19
6 Transition-based Reconfigurable FSM Reconfigurable Cell Focus on Transition Transition Row SSG: State Selection Gate ISM: Input Switching Matrix IPG: Input Pattern Gate NSR: Next State Register VHDL Silicon-proven Inputs ISM ISM ISM n I n T1 n T2 n Tm State n S SSG SSG SSG Clk En En En SR IPG IPG IPG NSR OPR NSR OPR NSR OPR Next State Select Outputs n O Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 6/19
7 Design Pre-Silicon Phase Define Application Class Specify Example Applications Common Denominator Pre-Silicon limits Post-Silicon Design Space Future Applications Might need more Resources Oversizing Additional Cell Instances Allow more Connections Application Class App 1 App 2 App 3 Reconfigurable Logic Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 7/19
8 Connection Topology Connection Types e.g. Bit, Byte, Word Requirements Random Connections Simple Characterization Allow Optimization Limit Optimization Oversizing Synthesizable Tree Topology Switch Switch Switch Switch C C C C C C C C Parallel Trees All Ports in all Trees Alternate Position Routing in any Tree Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 8/19
9 InterSynth: Overview Automatic Interconnect Generation and Optimization Pre-Silicon Input Example Netlists Cell Types Connection Types Output Synthesizable RTL Code Configuration Bitstreams Static Timing Analysis Rules LaTeX TikZ Image Internal Representation Post-Silicon Input Internal Representation Netlist Output Configuration Bitstream Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 9/19
10 InterSynth: Algorithm Degrees of Freedom Number of Cells per Type Interconnect Resources Mapping of Cells in Netlist ( Nodes ) to Physical Cells Placement of Physical Cells in Interconnect Tree Optimization Steps Optimize Cell Placement Node-to-Cell Mapping Repeat Until no Further Improvement Optimization Algorithm Modified Kernighan-Lin algorithm Optimization Goal Minimize Interconnect Resources Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 10/19
11 Digital Filters Application Class Simple Digital Filters Cell Types Adders Scalers Delays Netlists for Pre-Silicon biquad-df2 fir4-df1 fir4-df2 Extra Netlist for Post-Silicon biquad-df1 2 Parallel Interconnect Trees Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 11/19
12 Digital Filters Example Post-Silicon Netlist: biquad-df1 Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 12/19
13 Digital Filters Example Higher Order Filters Combine two Stages 16 different Netlists Pre-Silicon: 2-4 Examples enough Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 13/19
14 Full Design Flow Pre-Silicon Phase After InterSynth Synthesizable HDL Instantiate Cells Reconfigurable Routing SoC Integration Synthesis Place and Route Chip Input of InterSynth Example Netlists Cell Library App 1 App 2 App 3 Netlist 1 Netlist 2 InterSynth Synthesis P&R Netlist 3 SoC Cell Library Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 14/19
15 Full Design Flow Specification Easy to translate to netlist No new type of description Verifiable VHDL, Verilog Special Synthesis Coarse Grain Identify Cells FSM Extraction Bitstream Generation App 1 App 2 App 3 Netlist 1 Netlist 2 InterSynth Synthesis Netlist 3 SoC Cell Library P&R Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 15/19
16 yosys Yosys Open SYnthesis Suite Extensible RTL Synthesis Verilog (VHDL will follow) Coarse-grain and Fine-grain Focus on easy extensibility Preserve HDL Information Structure Frontend Multiple Passes Backend Currently under development Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 16/19
17 yosys Abstract HDL Constructs RTLIL RTL Intermediate Language Simple Internal Representation Modified by Synthesis Passes Passes Transformation of High-Level Constructs to Low-Level Constructs Optimization Coarse-Grain Mapping Passes Verilog HDL Code Frontend AST Representation AST Synthesis RTLIL Representation Backend Output Netlist Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 17/19
18 Full Design Flow Example Applications Coarse Grain Synthesis Cell Library Verification Simulation Equivalence Checking Wrapper Configuration Pre-Silicon Post-Silicon Sim EC Sim Sim Sim App 1 App 2 App 3 Netlist 1 yosys Coarse-Grain Mapping Netlist 2 InterSynth Synthesis P&R Netlist 3 SoC Cell Library Sim Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 18/19
19 Summary Ultra-Low-Power Electronics CPU Offload-Engines Reconfigurable Modules Interconnect Generation Coarse-Grain Synthesis Full Design Flow Future Work yosys VHDL Frontend More on Coarse-Grain Synthesis Computer Technology Wolf, Glaser, Schupfer, Haase, Grimm 19/19
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