ATMEL FPGA 3rd User Group Workshop. 2010, 3rd June Christophe POURRIER

Transcription

1 ATMEL FPGA 3rd User Group Workshop 2010, 3rd June Christophe POURRIER

2 Summary Sodern first experience with AT40K Megha-Tropiques Project PHARAO Project ATF280 Evaluation Tests performed on the first development kit ATF280E place and route capability Conclusion Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 2

3 Sodern experience Megha-Tropiques

4 Megha-Tropiques Satellite to scan tropical regions on the earth (meteo data) France-India scientific mission (CNES / ISRO) 3 instruments : SCARAB (optical sensor), SAPHIR and MADRAS (microwaves radiometer) SCARAB and SAPHIR are composed of two parts : a sensor or radiometer part and a calculator part SODERN in charge of SCARAB and SAPHIR calculators called Electronic Module : Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 4

5 Megha-Tropiques Each instrument : A Power Supply Board A CPU Board : ATMEL AT697E µp and SODERN ASIC from ATMEL MH1RT The C&C Board : 2 FPGA AT40KFL MQFP-160 and 2 EEPROM AT17LV10 Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 5

6 Megha-Tropiques 1srt FPGA, common for the 2 instruments : SpaceWire Link 3 clocks are used 20 MHz clock from a Quartz Oscillator 10 MHz clock for the Spacewire transmitter 12 MHz clock for the Spacewire receiver (24 Mbps) 1 derivated clock (receiver clock) is crossed back outside the FPGA on a dedicated input clock pin to guarantee the clock tree route Rmap and time code are excluded packets decoding PWM output signals processing data synchronization with the 2 nd FPGA (4 MHz clock) Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 6

7 Megha-Tropiques 2nd FPGA : 2 different designs (one for each instrument) : Packets decoding DAC control Servo-control data acquisition from DAC Telemetry acquisition from DAC Sensor / Radiometer sequencing Scientific data acquisition and processing (average) Data packaging for Spacewire packets Datation management with the Payload Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 7

8 Megha-Tropiques 1srt FPGA : 629 Cells = 30 % Maximum frequencies (Primetime): 2nd FPGA : 12 MHz Clock 30 MHz 20 Mhz clock 34 MHz 10 MHz clock 13 MHz Saphir : 1323 Cells = 57 % Scarab : 988 Cells = 42 % Maximum frequencies: Scarab Saphir 4 MHz Clock 9 MHz 9 MHz Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 8

9 Megha-Tropiques I/F available on the equipement to re-program the FPGAs through the EGSE Equipement Use of RS422 signal level to reprogram from a long distance RS422 signals Already used to upgrade the FPGA designs after new requirements (after equipment delivery to CNES) => very useful, no need of PPBI EGSE SCARAB instrument currently in India for Payload assembly SAPHIR instrument to be sent in the next few days to India Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 9

10 Sodern experience PHARAO

11 PHARAO Experience A cesium clock to fly aboard the International Space Station Scientific experience, prime ESA 4 parts : Cesium Tube, Laser Source, HF Source, Calculator UGB SODERN in charge of the Cesium Tube and the Laser Source Cesium Tube Laser Source Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 11

12 PHARAO Experience The Laser Source : 23 electronic boards Among these boards, a Digital Board centralizes data (telecommands and telemetries) The Laser Source (proto) Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 12

13 PHARAO Experience The Digital Board: 3 FPGA AT40KFL MQFP EEPROM AT17LV010 3 Proto Boards available today The Flight Model Board is about to be tested in the next few days Top Side of Proto Board Reverse side of Proto Board Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 13

14 PHARAO Experience The FPGAs are sequentially powered up to separate the peak current of each FPGA The common reset of the FPGAs is de-asserted when all the FPGA are configured The Designs : common 7.5 MHz clock common reset use of 4Kb of internal SRAM in the first FPGA Results : FPGA #1 FPGA #2 FPGA #3 Cells 37% 30% 30% RAM blocks 25% 0 0 IO Pads 71% 72% 79% 7.5 MHz clock 9 MHz 14 MHz 15 MHz Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 14

15 PHARAO Experience Need to implement 1000µF of capacitors to withstand the peak current at power-up. Use of internal Clamp Diode option to withstand 5V on input pads Use the Attribute GCLKBUF in VHDL code to force signal to a clock buffer gate. IBUFR macro in IDS have been removed since the IO does not work correctly. Only the IBUF macro is used. Problems in post-layout simulation with Modelsim: X signals => pb of double parenthesis : solved in IDS d timing violations with the RAM => solved in IDS We Use a batch file (.fbf). Problem to invoke pin and attributes files through the batch file. To be solved Only the EEPROM can be configured with the programmer tool CPS. It would be interesting to configure only the FPGA. It would be interesting to create macro functions in a batch file. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 15

16 ATF280 - Tests performed on the first development kit

17 ATF280 - Tests performed on the 1st dev kit Use of the Spacewire Link Analyser (SLA) (StarDundee) Test of LVDS Pads 2 Spacewire links in the FPGA (~5% of Cells) The 2 links are connected to a «Spy box» (SLA) Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 17

18 ATF280 - Tests performed on the 1st dev kit Ramp up time control is mandatory for the 1.8V core supply. We tried unsuccessfully to power on with a strong power supply (20A) : sink current raises up to 7A at power on. The start fails : the core voltage falls to 1.2V and the sink current remains at 4A. power on failure : 1: U-I/O 2: U-core 4: I-core Fortunately, the FPGA still works afterwards. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 18

19 ATF280 - Tests performed on the 1st dev kit Power supplies Scope 3.3V 1A U-I/O 1.8V 6A U-core PC I-core Spacewire Link Analyser Development kit Without a power generator with programmable voltage ramp up time, we perform the ramp manually (another solution : warm up the FPGA at 70 C). We use a power supply which provides up to 6A. When the power on is successful, the sink current falls to 10 ma (Atmel design is loaded in the FPGA). Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 19

20 ATF280 - Tests performed on the 1st dev kit The design is composed of 2 Spacewire codecs, driven by two packet generators. Data received are checked by two modules. Disconnections are displayed on leds. Input clock frequency is 10 MHz (the codecs use a 10-Mbit SDR transfer). Synthesis performed with Precision RTL. Place & route performed with Figaro IDS First test failed : the design does not work, we presume spacewire routed clocks were badly routed inside the FPGA. Second test is successful : spacewire clocks are crossed back outside the FPGA; they enter dedicated clock pins. The good operating conditions are checked thanks to the spacewire analyser: no error is recorded ; data characters per seconds are exchanged for each side 6,6 Mbit/s. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 20

21 ATF280 - Tests performed on the 1st dev kit Tests of frequency performance : the design frequency is increased thanks to the clock generator on the backplane board. Test result : 10 MHz : successful 20 MHz : successful 40 MHz : failed The 40-MHz test fails, probably due to external spacewire clocks routing. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 21

22 ATF280E place and route capability

23 ATF280E place and route capability implementation test of SODERN s processor companion chip design (EU-ASIC) on the FPGA : the design is composed of : x1 PCI controller with a DMA engine (PLDA source) x Remote Terminal (Astrium source) x1 base of registers x4 Spacewire codec x1 ASCS16 controller others modules (Pwm, IT controller, delta-sigma conversion, ) Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 23

24 ATF280E place and route capability implementation of the EU-ASIC design on the FPGA : synthesis result : C-Cells : 180 % R-Cells : 29 % Ram blocks are set as black boxes The synthesis seems not be optimized, since C-Cells and R-Cells are separated. There is no R+C Cell assessment, whereas the ATF280E owns a single kind of cell based on a flip-flop and LUT elements. The whole design does not fit (180% of C-cells). Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 24

25 ATF280E place and route capability implementation of each modules separately of the EU-ASIC design on the FPGA ; Place & Route results are extracted after IDS compilation. Synthesis results Place & Route Results C-cells R-Cells Cells 32x4 RAM blocks PCI controller % 24 3% ASCS16 controller % 0 0% 1553 Remote Terminal % % SpaceWire codec % % Base of registers % 28 3% DMA PCI Engine % 36 4% March codec % 0 0% others % 0 0% TOTAL % % P&R Cells are less numerous than Synthesis C-Cells or R-Cells, which show IDS may optimize synthesis result by concatenating R Cells and C Cells. Total : 147 % of cells ; 78 % of RAM blocks. Assessment is less than synthesis results, but it is about 150%. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 25

26 ATF280E place and route capability implementation of dedicated design: a large RAM in the FPGA synthesis and a complete place and route are performed to assess place and route capability. the RAM is a synchronous dual port RAM with two address bus, two 32-bit data bus, a single clock, write and read commands. Cells number Cells % RAM blocks RAM % Place & route result 32-Kbit RAM (1Kx32) % % successful 64-Kbit RAM (2Kx32) % % successful 82-Kbit RAM (2.5Kx32) % % failed Place and Route capability is limited : we estimate the 64-Kbit RAM has nearly reached the maximum place and route capability. Since P&R is limited for RAM, this may reduce P&R capability for Cells. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 26

27 ATF280E place and route capability implementation of a large design in the FPGA : synthesis and a complete place and route are performed to assess place and route capability. the design is composed of 3 independent parts : two 1553 remote terminal and one 64-Kbit dual port RAM. RAM Place & route Cells number Cells % blocks RAM % result % % successful The place & route is successful. It takes about 5 hours for IDS to achieve place and route. The place route capability is limited : we estimate the present design has nearly reached the maximum place and route capability. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 27

28 ATF280E place and route capability ATF280E versus RTAX2000S with the same design EU-ASIC: Cells Cells % RAM blocks RAM % RAX2000S / % 54 / 64 84% ATF280E / % 704 / % With a place & route capability of 50%, we estimate the ATF280E is 1/5 of RTAX2000S concerning Logic cells. Concerning RAM, the ATF280E offers a better arrangement of RAM : data length is arranged by step of 4 bits instead of 9 bits for small RAM (depth <512) in RTAX2000S, which avoids bit waste. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 28

29 Conclusion

30 ATF280E conclusion Sink current reaches 7A at power on => solved in the next silicon (to be tested on the new dev board) The ATF280E has the same problem of routed clocks distribution as the AT40KFL040. External loop back is a solution for low frequencies (below 20 MHz) but can not be performed for high frequencies. LVDS I/O operate correctly without specific resistances to drop the voltage level (to compare with Altera FPGA). Place and route is limited : we estimate 50% of Cells and 50% of RAM is the limit to provide an easy re-configurability (even if better rate can be achieved on a case by case basis). Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 30

31 ATF280E conclusion ATF280E logic resources covers 1/5 of a RTAX2000S (place & route capability included). ATF280E offers a good arrangement of Free RAM which avoids bit waste. The design EU-ASIC can not fit in the ATF280E : better fit is possible by optimizing large modules. A long time for design development must be taken into account. Next step : test of the new silicon on the new dev kit. Titre de la présentation Auteur 07/06/2010 EADS SODERN Confidential-SODERN s Intellectual property-all rights reserved 31

32 Thank you for your attention