on-chip and Embedded Software Perspectives and Needs

Transcription

1 Systems-on on-chip and Embedded Software - Perspectives and Needs Miguel Santana Central R&D, STMicroelectronics STMicroelectronics

2 Outline Current trends for SoCs Consequences and challenges Needs: Tackling SoC design complexity Needs: Embedded software development 2

3 Outline Current trends for SoCs Consequences and challenges Needs: Tackling SoC design complexity Needs: Embedded software development 3

4 Market size for different sectors 2000 Electronics 4

5 Market size for different sectors TGV+Satellite launchers 2005 Military Aircrafts Civil Aviation Semiconductors Petroleum exportations 5

6 Convergence: Voice,, Data, Multimedia Media-Centric Game MP3 Player Imaging Phone Web Pad Voice-Centric Smartphone Communicator PDA Notebook Data-Centric 6

7 Example: wireless applications HW/SW functions inside 3G phones 2.5G baseband function 3G WCDMA baseband Multimedia engine (MPEG4, MP3..) OS processor GPS / Bluetooth / engine DTV 7

8 Moore s law and price evolution Microelectronic functions are one million times less expensive than in the 70 s euros Megabit price euros 400 euros 120 euros 30 euros 1973 Source: Siemens euros 0,5 euro0,05 euro

9 SoC at the heart of conflicting trends Time-to-market: Process roadmap acceleration Consumerization of electronic devices Link FEI Dolby AC3 Denc ST20 MPEG2 Video Complex systems: ucs, DSPs HW/SW SW protocol stacks RTOS s Digital/Analog IPs On-Chip busses 2 x 3 DAC Deep sub micron effects: crosstalk electro migration wire delays mask costs (OPC, PSM) 9

10 Outline Current trends for SoCs Consequences and challenges Needs: Tackling SoC design complexity Needs: Embedded software development 10

11 The Design Productivity Gap Logic Transistors per Chip (M) Logic Transistors per Chip (M) Productivity (K)Trans./Staff-Mo. Productivity (K)Trans./Staff-Mo CAGR 58% Production CAGR 21% Design Source ITRS roadmap

12 10 12 Embedded Software more critical Gates/chip: 2x / 18 months SW/Chip: 2x / 10 months SW productivity: 2x / 5 years % / year +140% / year Lines of code Gates 12

13 The Verification Gap x more vectors required to validate 100x / 6 years 10B 100M 1M k 1M 10M 100x Gate Count 100 x = 1 million times more simulation load 10x / 6 years 13

14 Low Power Requirements System Level Architecture Power/Performance trade-off Memory size and bandwidth optimization Code optimization Quality of Service Disk Drive Controller HCMOS8 0.18um RTL to Layout Activity control Gated clock Power based synthesis Leakage control Supply control Mix High-Speed and Low-Leakage libs HCMOS8 ST20 / ST40 Smart Power/Low-voltage operation Multi-voltage support On-chip voltage regulator(s) 0.25um BiCMOS GSM Power Mgnt 14

15 Miscellaneous Increasing number of embedded processors No longer 1 or 2, but Heterogeneous processors in many cases Managing parallelism Real-time SW working with the HW Managing threads/tasks in a real-time environment Verifying the right behavior Increasing cost of masks 15

16 Outline Current trends for SoCs Consequences and challenges Needs: Tackling design complexity Needs: Embedded software development 16

17 Closing the gap 1000 CAGR 58% Logic Transistors per Chip (M) Logic Transistors per Chip (M) Productivity (K)Trans./Staff-Mo. CAGR 21% System Level Specification RTL-to-Layout HW-SW co-design IP Reuse Low Power Libraries 0.01 Analog-Mixed Signal

18 Tools for SoC Designers System spec. HW/SW partitioning H/W CAD flow Co-design S/W CAD flow IO LOGIC Analog RF Place & route Code Core Data I O LOGIC Data Code Core Processor Analog RF 18

19 Platform-Based SoC Design 2D graphics MPEG2 video decoder DRAM/SRAM Configurable STBus ROM/OTP FLASH Glue Logic Standard I/O blocks D/A, A/D Reconfigurable Platform e.g: Set-Top Box Display coprocessor 3D processor MMDSP+ ST20/40 uprog peripherals Analog ASIC Proc MPEG2 decoder Display coprocessor SRAM Configured STBus MMDSP+ FLASH ST20 Glue Logic Firewire D/A, A/D S/W S/W F/W uprog peripherals Customer1 Specific Product SW customization HW Blocks Selection Bus Configuration Memories MPEG2 decoder 3D processor SRAM Configured STBus MMDSP+ S/W ROM ST40 S/W Glue Logic Firewire D/A, A/D uprog peripherals F/W Customer2 Specific Product 19

20 Composing an architecture Configuration items Decomposed application Configurable hw platform SoC 20

21 Configurable processors Configurable core Application specific instructions Execution units Parameterized control unit Coprocessors Software/hardware marriage Compiler friendly Synthesis friendly Standard interfaces Control Communication ALU 1 Memory MAC Unit ALU 2 Address Unit Config. core processor Shifter Co processor... 21

22 Outline Current trends for SoCs Consequences and challenges Needs: Tackling design complexity Needs: Embedded software development 22

23 Hardware vs Embedded Software Log (Number of lines/gates) Systems-on-Chip Chip composition Embedded Software Hardware

24 Progress Achieved Embedded software development Migration to high-level languages High-quality code generation Improvement of processor I/S Interaction with HW development Better support for HW platforms Integration with HW design tools Support for performance evaluation Accurate processor modeling 24

25 Unresolved Issues Orthogonal embedded processors Irregularities (encoding, registers, ) Specific features Optimizing compilers for embedded software Code size improvement Memory optimization Optimization interaction Adopt/adapt new optimization methods Tool integration Plug-in modules 25

26 Converging HW/SW CAD flows System specification Operational Constraints Configurable platform Hardware / software partitioning Architectural choices Software coding Tools: analysis and synthesis architecture application OS communications System: hardware + software (correct by construction) Functional and temporal tests OK KO + diagnostic 26

27 Compilers and SoCs Keystone for embedded software development Synthesizing application code into processor I/S Exploiting processor features Optimizing code and resource usage Driving processor architecture evolution Compiler as a CAD tool for SoCs Compiling for a HW platform (instead of a processor) Assisting SoC architects Automating some choices Interactive work with designers Application analysis feedback Case-based reasoning Managing real-time aspects Compiler Application Architecture 27

28 Embedded real-time software Support for temporal constraints Specification, modeling, coding, verification Respecting real-time constraints Synthesis of embedded real-time code Static or dynamic scheduling RTOS generation Verifying temporal constraints Modeling application environment Generation of test scenarios Performance evaluation Not max but average performances WCET 28

29 Other topics System debugging Monitoring distributed systems Observing system evolution Configurable RTOS Customized for application needs Evolution of embedded system developers Mixed software/hardware profile Physical design knowledge Multiprocessing 29

30 Backup slides 30

31 Requirements Requirements specification, representation Analysis (cost, schedule, scope) Allocation, partitioning Spec/Design Languages + Modeling Fundamentals Functionality and constraints specification Specification formalisms (formal) Heterogeneity, emerging languages System Design System design conceptual model(s) Design processes/methodology (refinement, validation, constraint propagation, performance evaluation, integration, guidelines) Environment: Distributed Design System Architecture Design space exploration Performance evaluation (quality estimation) System environment description Architecture Description Language Low Power Architecture Synthesis Platform Design Platform modeling Mapping of spec on given platform Product vs technology platforms Reconfigurability/Scalability Programmability Research Domains System IP reuse 31 Reuse/integration of know-how, methods, algorithms, solutions Repository of assets Encapsulation, Interfaces (IF-based design) System Analysis/Estimation (Quality) Functionality vs Architecture Performance analysis / computing (accuracy) High-speed, Low-power, Fault tolerance, RT Automated support Validation/Verification/Testing Validation: requirements, standards Verification: static/dynamic, formal, safety Testing: hierarchical, model-based Reliability Embedded SW reuseable, scalable, flexible, optimised SW architectures, operating systems (RT) Analog, RF, Microsystems Interfacing, performance, reconfiguration Link to Implementation Integration of reconfigurable cores HW/SW Co-design, autom. synthesis, verif Mixing C/HDL models Interconnect driven chip design Best Practice EDA Support, Quality, Standards Training Model design engineers