Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai Jens Onno Krah

Transcription

1 (DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences NIOS II 1 1 What is Nios II? Altera s Second Generation Soft-Core 32 Bit RISC Microprocessor - Nios Developed II Plus Internally All Peripherals By Altera Written In HDL - Can Harvard Be Targeted Architecture For All Altera FPGAs - Synthesis Royalty-Free Using Quartus II Integrated Synthesis Nios II CPU Debug On-Chip ROM On-Chip RAM Cache Avalon Switch Fabric UART GPIO Timer SPI SDRAM Controller NIOS II 2 FPGA

2 Problem: Reduce Cost, Complexity & Power I/O I/O I/O CPU I/O I/O I/O FPGA Flash SDRAM DSP CPU DSP Solution: Replace External Devices with Programmable Logic NIOS II 3 FPGA Hardware Design Flow Design Specification LE M4K M512 I/O Design Entry/RTL Coding - Behavioral or Structural Description of Design SOPC Builder RTL Simulation Functional Simulation (Modelsim, - Simulation (Modelsim, Quartus II) Quartus II) Verify Logic Model & Data Flow - Verify Logic Model & Data Flow (No Timing Delays) (No Timing Delays) Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Spectrum, Synplify, Quartus II NIOS II 4 Place & Route - Map Primitives to Specific Locations Inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used

3 FPGA Hardware Design Flow t clk Timing Analysis - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology Test FPGA on PC Board - Program & Test Device on Board - Use SignalTap II for Debugging NIOS II 5 DBC2C20 NIOS II Development Kit USB OTG 2x CAN Phy RS232 Phy 24pin 3V3 GPIO 4x RS485 Phy Download /JTAG Debug Connector Temperature Sensor 16 MB SDRAM Power Connector 8 MB Flash 24V I/O Buttons 7-Segment Anzeige LEDs Power LED LVDS I/O NIOS II 6 10/100 Ethernet PHY & RJ-45 Connector

4 Reference Designs For Dev Kits Several reference designs are available See altera\kits\nios2.60\examples\verilog or altera\kits\nios2.60\examples\vhdl NIOS II 7 Standard Design Block Diagram 8MB FLASH 16MB SDRAM RS232 Driver RS485 Driver Nios II Processor 32-Bit Nios II Processor IRQ IRQ Address (32) Read Write Data In (32) Data Out (32) Avalon Switch Fabric Tri-State Bridge ROM (with Monitor) LED PIO SDRAM Controller General Purpose Timer Button PIO UART Periodic Timer GPIO UART Ethernet 10/100 MAC CAN Ethernet Phy On-Chip Off-Chip 3 LEDs Buttons Header CAN Driver NIOS II 8

5 Nios II System Architecture Nios II CPU On-Chip Debug Core Off-Chip Software Trace Memory Instr. Data NIOS II 9 Address Decoder Interrupt Controller Wait State Generation Data in Multiplexer Master Arbitration Dynamic Bus Sizing Avalon Master/ Slave Port Interfaces Avalon Switch Fabric UART 0 UART n Timer 0 SPI 0 GPIO 0 DMA 0 Memory Interface Timer n SPI n GPIO n DMA n Memory Interface InterfaceUser-Defined Interface Nios II Processor Architecture Classic Pipelined RISC Machine 32 General Purpose Registers 3 Instruction Formats 32-Bit Instructions 32-Bit Data Path Separate Instruction and Data Cache (configurable sizes) Branch Prediction 32 Prioritized Interrupts Custom Instructions JTAG-Based Hardware Debug Unit NIOS II 10

6 Nios II Block Diagram JTAG interface to Software Debugger reset clock Hardware- Assisted Debug Module Nios II Processor Core Program Controller & Address Generation General Purpose Registers r0 to r31 Instruction Cache Instruction Master Port irq[31..0] Custom I/O Signals Custom Instruction Logic Exception Controller Interrupt Controller Arithmetic Logic Unit Control Registers ctl0 to ctl4 Data Cache Data Master Port NIOS II 11 Nios II Versions Nios II Processor Comes In Three ISA Compatible Versions FAST: Optimized for Speed STANDARD: Balanced for Speed and Size ECONOMY: Optimized for Size Software Code is Binary Compatible No Changes Required When CPU is Changed NIOS II 12

7 Binary Compatibility / Flexible Performance Nios II /f Fast Nios II /s Standard Nios II /e Economy Pipeline 6 Stage 5 Stage None H/W Multiplier & Barrel Shifter 1 Cycle 3 Cycle Emulated In Software Branch Prediction Dynamic Static None Instruction Cache Configurable Configurable None Data Cache Configurable None None Logic Usage (Logic Elements) Custom Instructions Up to 256 NIOS II 13 Hardware Multiplier Acceleration Nios II Economy version - No Multiply Hardware Uses GNUPro Math Library to Implement Multiplier Nios II Standard - Full Hardware Multiplier 32 x in 3 Clock Cycles if DSP block present, else uses software only multiplier Nios II Fast - Full Hardware Multiplier 32 x in 1 Clock Cycles if DSP block present, else uses software only multiplier Acceleration Hardware Clock Cycles (32 x 32 32) None 250 Standard MUL in Stratix Fast MUL in Stratix 3 1 NIOS II 14

8 Hardware Multiplier Support Stratix and Stratix II DSP Blocks Cyclone II Multiplier Blocks Multiplication using 18 x 18 Multiplier Block Optional LE Implementation Enables HW multiplier support for Cyclone Device Family Can also use in Stratix and Stratix II instead of DSP Blocks Mul, Shift, Rotate (~ 8 Clocks Per Mul) Eliminates need for DSP blocks for Nios II MUL NIOS II 15 Variation with FPGA Device Fast DMIPS Standard 50 Economy Logic Elements Stratix II Stratix Cyclone HC-Stratix NIOS II 16

9 SOPC Builder - System Contents IRQ Priorities Connection Panel Address Map Clock Domains Component NIOS II 17 Insert Peripherals Including Nios II Processor Double-click on peripheral or press Add Build up memory map of your embedded system Eg. System Memory Space 0x SDRAM Other Peripherals 0x x NIOS II 18 Flash 0x0

10 Quartus II Project Directories Hardware HDL Source & Netlist db - Quartus project database Software Application source code Library files Simulation ModelSim project Automatically generated test memory and vectors All other Quartus II and SOPC Builder System files NIOS II 19 SOPC Builder Flow Processor Library SOPC Builder GUI Configure Processor Custom Instructions Peripheral Library Hardware Development HDL Source Files Testbench Select & Configure Peripherals, IP Connect Blocks Generate IP Modules Software Development Nios II IDE C Header files Custom Library Peripheral Drivers Synthesis & Fitter Hardware Configuration File Verification & Debug Executable Code Compiler, Linker, Debugger User Design Other IP Blocks Quartus II NIOS II 20 Altera PLD JTAG, Serial, or Ethernet On-Chip Debug Software Trace Hard Breakpoints SignalTap II User Code Libraries RTOS GNU Tools

11 Running Code On A Target Nios II IDE can be used to download code to target board NIOS II 21 Running Code On A Target Download messages, stdout and stdin appear in console window NIOS II 22

12 System ID Peripheral Revisited When downloading code to a target, Nios II IDE computes expected System ID peripheral values from PTF file If computed ID values do not match System ID variables stored on the target board then an error is flagged Generally, to fix this you should recompile your hardware To disable this option see Run > Run Main Page NIOS II 23 Avalon Switch Fabric Proprietary interconnect specification used with Nios II Principal design goals Low resource utilization for bus logic Simplicity Synchronous operation Transfer Types Slave Transfers Master Transfers Streaming Transfers Latency-Aware Transfers Burst Transfers Nios II Processor 32-Bit Nios II Processor ROM (with Monitor) IRQ IRQ #(6) UART Address (32) Read Write Data In (32) Data Out (32) Timer Avalon Switch Fabric Switch PIO LED PIO 7-Segment LED PIO PIO-32 User- Defined Interface NIOS II 24

13 Nios II - Leads The Industry Highest Performance Multi-Processor Hardware Acceleration Custom Instructions Greatest Flexibility Most Powerful Design Tools Fastest Time to Market Processors Peripherals Optimized Interconnect SOPC Builder Nios II IDE On-Chip Processor Debug SignalTap II Logic Analyzer Concept to System in Minutes FPGA > HardCopy Structured ASIC NIOS II 25