Optimizing Configuration and Application Mapping for MPSoC Architectures

Transcription

1 Optimizing Configuration and Application Mapping for MPSoC Architectures École Polytechnique de Montréal, Canada Sebastien.Le-Beux@polymtl.ca 1

2 Multi-Processor Systems on Chip (MPSoC) Design Trends SoC Design two contradictory trends Rising platform development cost Reducing the product market window Directions to tackle these challenges Exploit domain-specific MPSoC reusable platforms Several interconnected processors Networks-on-Chip Proc 1 Proc 2 Proc n Network-on-Chip 2

3 Multi-Processor SoC (MPSoC) Design Trends System-on-Chip (SoC) Higher performance More Moore System-in-Package (SiP) Extended functionalities More Than Moore 3D Integration Combining SoC and SiP Logic transistors per chip (in millions) Note: logarithmic scale 10,000 1,

4 Multi-Processor SoC (MPSoC) Design Trends System-on-Chip (SoC) Higher performance More Moore System-in-Package (SiP) Extended functionalities More Than Moore 3D Integration Combining SoC and SiP Source : Balinga, Banerjee 4

5 Multi-Processor SoC (MPSoC) Design Trends System-on-Chip (SoC) Higher performance More Moore System-in-Package (SiP) Extended functionalities More Than Moore 3D Integration Combining SoC and SiP 5

6 Multi-Processor SoC (MPSoC) Design Trends 3D Integration Technology Promising paradigm for Heterogeneous Systems Multiple tiers multiple technologies Functions will use the best technology available Ex. computing electronics / communication optics Optical Layer Electric Layers Proc 1 Proc 2 Proc n Network-on-Chip 6

7 Configuration Parameters in MPSoC Design No. of proc. in the architecture No. of layers (tiers) Type of Network on Chip Technology used for each layer Application Mapping T1 T3 T5 T7 T9 T0 T11 T2 T4 T6 T8 T10 Proc 1 Proc 2 Proc n Network-on-Chip 7

8 Challenges for MPSoC Design Huge solutions space System-level approaches for design-space exploration are mandatory T1 T3 T5 T7 T9 T0 T11 T2 T4 T6 T8 T10 Proc 1 Proc 2 Proc n Network-on-Chip 8

9 Outline System-Level Approach for Optimizing Configuration and Application Mapping for MPSoC Architectures Case Studies Conclusions 9

10 System-Level Exploration Flow Application Model T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Optimization Metrics Architecture Model Proc 1 Proc 2 Proc n Network-on-Chip Multi-Objective Optimization - exploration engine - Performance Analysis Set of Pareto Solutions Promising Mappings and Configurations Visualization & Debug 10

11 Application Model Streaming Applications Regular and repeating computations Explicit parallel, independent computations Explicit communication T1 T3 T5 T0 T2 T4 T6 T7 T8 T9 T10 T11 11

12 Application Model Directed acyclic graph G = (T,E) T set of tasks Annotated with an execution time Expressed in no. of Clock Cycles (cc) required for the execution E - set of edges Annotated with the amount of data transferred between the tasks connected by the edge Expressed in bytes (b) T1 T3 T5 T7 T9 T0 T kcc 12 kb 12 kb T2 537 kcc 537 kcc 16 kb 16 kb 536 kcc 268 kcc T4 24 kb 24 kb T6 T8 268 kcc 268kcc T kcc 268 kcc 28 kb 28 kb 536 kcc 536 kcc 32 kb 32 kb 24 kb 24 kb 100 kcc 12

13 System-Level Exploration Flow Application Model T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Optimization Metrics Architecture Model Proc 1 Proc 2 Proc n Network-on-Chip Multi-Objective Optimization - exploration engine - Performance Analysis Set of Pareto Solutions Promising Mappings and Configurations Visualization & Debug 13

14 Architecture Model Planar Architectures Set of Nodes interconnected through a Network-on-Chip (NoC) Node - a subsystem including a processor and its local memory NoC - composed of a set of Links and Switches Mainly bandwidth (streaming) 3x3 MESH 14

15 Architecture Model: 3D MESH 3D MESH Architectures Extrapolation of existing planar architectures Switches adapted for vertical routing Interconnection types Intra-layer Inter-layer 15

16 3D MPSoC Including Optical Networks-on-Chip (ONoC) Architecture defined by extrapolation of 2 planar approaches : 1. Electrical Network on Chip 2. Optical Network on Chip Wavelength Division Multiplexing (WDM) Low latency (<1 ns) Limited by optical/electrical interfaces Objectives: exploration of the design space by considering technological constraints 16

17 3D MPSoC Including Optical Networks-on-Chip Optical Network Interface (ONI) receiver driver SER Interconnect Ratio IR = No of ONI Total No of Nodes 17

18 System-Level Exploration Flow Application Model T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Optimization Metrics Architecture Model Proc 1 Proc 2 Proc n Network-on-Chip Multi-Objective Optimization - exploration engine - Performance Analysis Set of Pareto Solutions Promising Mappings and Configurations Visualization & Debug 18

19 Optimization Metrics 1. Execution time 2. Critical Delay 3. Area cost 19

20 Optimization Metrics 1. Execution time The time required to execute a complete iteration of an application 20

21 Optimization Metrics 1. Execution time 2. Critical Delay The delay between executions of application iterations Defines the throughput of the system 21

22 Optimization Metrics 1. Execution time 2. Critical Delay Communication oriented event-based simulator 22

23 System-Level Exploration Flow Application Model T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Optimization Metrics Architecture Model Proc 1 Proc 2 Proc n Network-on-Chip Multi-Objective Optimization - exploration engine - Performance Analysis Set of Pareto Solutions Promising Mappings and Configurations Visualization & Debug 23

24 Exploration Engine Automatic multi-objective optimization Exploits evolutionary algorithms Chromosome-like representation 24

25 Combining Mapping and HW- SW Partitioning 25

26 Outline System-Level Approach for Optimizing Configuration and Application Mapping for MPSoC Architectures Case Studies Conclusions 26

27 Demosaic Image Processing Application 27

28 Mapping Demosaic Application on Planar Architectures 28

29 Mapping Demosaic Application on Planar Architectures 29

30 Mapping Demosaic Application on 3D Architectures 30

31 ONoC Design Feasibility for Two Layers Architectures 31

32 Conclusions Optimizing Configuration and Application Mapping for MPSoC Architectures System-level Automated Case studies Configuration of planar and 3D MPSoC architectures Demosaic application T1 T3 T5 T7 T9 T0 T11 T2 T4 T6 T8 T10 Proc 1 Proc 2 Proc n Network-on-Chip 32

33 Optical Network-on-Chip wavelength matrix network topology 33

34 Throughput performances (random traffic generation) 34

35 Multi-ONoC 35

36 Multi-ONoC Layout 36