Eingebettete Systeme. 4: Entwurfsmethodik, HW/SW Co-Design. Technische Informatik T T T

Transcription

1 Eingebettete Systeme 4: Entwurfsmethodik, HW/SW Co-Design echnische Informatik

2 System Level Design: ools and Flow Refinement of HW/SW Systems ools for HW/SW Co-Design C-based design of HW/SW Systems echnische Informatik Eingebettete Systeme F 2015, Kap. 4 2

3 V-Diagram Architecture Exploration Problems: 1.) Specification often unclear/informal 2.) ime from specification to validation too long! echnische Informatik Eingebettete Systeme F 2015, Kap. 4 3

4 Concurrent engineering of HW and SW Specification HW Design Prototype SW Develop. System Integration echnische Informatik Eingebettete Systeme F 2015, Kap. 4 4

5 Executable Specification and Virtual Prototyping Executable specification Architecture exploration (Development of HW+SW) System integration, Integration validation Virtual prototyping instead of HW prototyping echnische Informatik Eingebettete Systeme F 2015, Kap. 4 5

6 Executable specification Specification in a form that can be simulated High-level simulation (Matlab, C/C++, SystemC, ) Purpose Check correct understanding of specification Get insight into system behavior Starting point of design Comparision with design echnische Informatik Eingebettete Systeme F 2015, Kap. 4 6

7 Instruction Set Simulator/Virtual Prototype Instruction Set Simulator (ISS) Simulator that executes SW on a simulated processor Required for debugging/analysis of SW, if no processor HW is available 1. Binary compatible important, if OS (Linux, ) contributes to behavior 2. C-Code compatible faster, because it is compiled to host processor Example: VAS ( Virtual Prototype Software model of designed HW (more general than ISS, includes additional HW) Developed by HW developers for SW development Should be available before SW development starts Should be easy-to-use Shared library, IDE for SW developers echnische Informatik Eingebettete Systeme F 2015, Kap. 4 7

8 Parallel developement/debugging of HW and SW Executable Specification ( C / C++ / UML ) Development of Hardware ISS, Virtual Prototype Development of Software Redesign Verification System Integration Redesign ASIC Design or FPGA Synthesis echnische Informatik Eingebettete Systeme F 2015, Kap. 4 8

9 Issues of architecture exploration Evaluation of design decisions Board / ASIC Adaptive/Fixed partioning HW/SW partitioning ype of processor Co-Processor Bit-widths Sample frequencies Buffer sizes Specification of control signals, bus protocols, interfaces echnische Informatik Eingebettete Systeme F 2015, Kap. 4 9

10 Step-wise refinement of HW and SW Executable Specification ( C / C++ / UML ) Programmer s view (for basic SW dev.) Development of ISS, Virtual Prototype iming & Performance (for architecture eval.) Hardware Pin accurate (for integration verification) Development of Software Redesign Integration Verification ASIC Design o. FPGA Synthese Redesign echnische Informatik Eingebettete Systeme F 2015, Kap. 4 10

11 Concurrent engineering of HW and SW (2) Specification HW Design Prototype SW Develop. System Integration With refinement, it can be done in parallel! Specification Virtual Prototype HW Design SW Develop. System Integration echnische Informatik Eingebettete Systeme F 2015, Kap. 4 11

12 System Level Design: ools and Flow 1. Refinement of HW/SW Systems 2. C-based design of HW/SW Systems 3. Some commercial tools for HW/SW Co-Design echnische Informatik Eingebettete Systeme F 2015, Kap. 4 12

13 Why C-based design of embedded systems? Software and methods: C/C++, UML, Hardware: VHDL, Verilog, SPICE, System design Software Evaluation, Analysis requires simulator coupling or translation Hardware Implementation C, C++, UML, VHDL, Verilog echnische Informatik Eingebettete Systeme F 2015, Kap. 4 13

14 Why C-based design of embedded systems? C-Based modelling is a pragmatic approach System design Software C, C++, UML, + Modelling of time, concurrency, HW-Signal types Hardware Implementation C, C++, UML, VHDL, Verilog echnische Informatik Eingebettete Systeme F 2015, Kap. 4 14

15 C-based approaches many approaches in research and industry Well-known C-extensions are: SpecC (Gajski et al. ; UC Irvine) Pre-compiler generates C code and Parameterizable architecture model from SpecC Good for design space exploration SystemC OSCI Standard = Open SystemC Initiative, now ACCELLERA Fujitsu, Motorola, Intel, Infineon, S, AMD, NXP, Synopsys, Cadence, Proof-of-concept prototype free: echnische Informatik Eingebettete Systeme F 2015, Kap. 4 15

16 Eingebettete echnische Informatik Systeme F 2015, Kap. 4 16

17 Use of SystemC SystemC Model SystemC library C ++ Compiler and Linker executable code (=Simulator) C ++ Debugger Waveform viewer echnische Informatik Eingebettete Systeme F 2015, Kap. 4 17

18 System Level Design: ools and Flow 1. Refinement of HW/SW Systems 2. C-based design of HW/SW Systems 3. Some commercial tools for HW/SW Co-Design echnische Informatik Eingebettete Systeme F 2015, Kap. 4 18

19 ool Requirements Instruction Set Simulator for CPU available? Important factor, often exclusion argument. Correctness of Instruction Set Simulators? Important for fault coverage. Compatible with SW engineering tools? Support for SW Debugger, ROS,... Performance of simulation? Important for short design cycles. Instruction Set Simulator Performance? Not that important, normally fast enough. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 19

20 ools from academia VULCAN: Stanford University (Hardware C) COSYMA: University of Braunschweig (Cx) POLIS: University of California Berkeley (C++, SystemC) POLEMY: University of California Berkeley (C++, Java) echnische Informatik Eingebettete Systeme F 2015, Kap. 4 20

21 Commercial tools Mentor Seamless supports a plethora of CPU models integrated with ModelSim Synopsys CoCentric System Studio SystemC development platform CoWare SPW, CoWare Lisatek SPW: Signal Processing Workstation echnische Informatik Eingebettete Systeme F 2015, Kap. 4 21

22 CoWare SPW HW/SW Co-Design IDE Fully integrated, from spec to silicon! On each abstraction level all blocks have multiple views of its definition. Complete simulation environment. A large range of stimulus generators for test bench development. Parameter extraction from transistor level for generating high level models of design units. Interface to LISAek, a processor development tool. Source: echnische Informatik Eingebettete Systeme F 2015, Kap. 4 22

23 Source: echnische Informatik Eingebettete Systeme F 2015, Kap. 4 23

24 Source: echnische Informatik Eingebettete Systeme F 2015, Kap. 4 24

25 CoWare LISAek Processor Development ool IDE for developing processor units. Generates the complete RL description of the processor with its toolset like compiler, linker, and the instruction set simulator! Only needs an abstract processor description, and the user application. Source: echnische Informatik Eingebettete Systeme F 2015, Kap. 4 25

26 Summary he aim of a good HW/SW Co-design flow is to enable concurrent development of HW and SW Virtual prototype, Instruction set simulator Refinement C-Based design enables seamless HW/SW design Commercial tools solve some specific tasks, but no really seamless flow available echnische Informatik Eingebettete Systeme F 2015, Kap. 4 26

27 Verification Verification What is it, how it is done? HW/SW Co-Verification What is this? ools For HW/SW Co-Verification Verification Challenges Future problems with verification Formal Verification Binary Decision Diagram echnische Informatik Eingebettete Systeme F 2015, Kap. 4 27

28 Verification I What is Verification? Used to ensure the correctness of the design against its intended behavior (the specification) against its implementation (at different abstraction levels) against alternative design (at the same abstraction level) high abstraction level low layout structural functional behavioral Architecture Design Implementation A?? 7.) Mask Level 6.) Place & Route 5.) Gate Level Netlist 4.) Silicon Compilation 3.) RL Description 2.) Architecture Extraction 1.) System Description echnology Idea??? Design Implementation B? 7.) Mask Level 6.) Place & Route 5.) Gate Level Netlist 4.) Silicon Compilation 3.) RL Description 2.) Architecture Extraction 1.) System Description echnische Informatik Eingebettete Systeme F 2015, Kap. 4 28

29 Verification II In contrast to the prevailing view by much of the semiconductor industry, verification has become the dominant cost in the design process! Verification engineers outnumber designers by a factor two to three for most complex designs. Design conception and implementation are becoming mere preludes to the main activity of verification! Verification needs raises exponentially with the system complexity (which itself raises exponentially), resulting in a verification crises. Automated verification methods are becoming much more important. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 29

30 Verification III Examples of undetected errors Pentium bug multiplier table not fully verified, cut and paste failure of the engineer Ariane V rocket explosion exception occurred during conversion of a 64-bit floating point number to a 16-bit integer since the magnitude of the value changed due to design re-use Mars Climate Orbiter lost incorrect usage of English units instead of SI units resulted in orbiter crash echnische Informatik Eingebettete Systeme F 2015, Kap. 4 30

31 Verification IV Verification Methods Simulation performed on a model Formal Verification heorem proving Equivalence checking Model checking Prototyping Emulation esting performed on the actual product Manufacturing test echnische Informatik Eingebettete Systeme F 2015, Kap. 4 31

32 HW/SW Co-Verification I Event or cycle based simulations are for System on Chip designs too slow need for special HW/SW Co- Verification tools! + Source: Mentor Graphics echnische Informatik Eingebettete Systeme F 2015, Kap. 4 32

33 HW/SW Co-Verification II What is HW/SW Co-Verification? A methodology used for System on a Chip Designs. Allows concurrent verification and debugging of hardware and software. he used tools are familiar to the hardware engineer as well as to the software engineer. Is a technology which increases the simulation performance without scarifying the correctness of the simulation. How is this achieved? By integrating an Instruction Set Simulator (about instructions per second) into the system simulation model. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 33

34 HW/SW Co-Verification III Requirements CPU is replaced with a Bus Interface Model (BIM) which establishes the interface to the Instruction Set Simulator. All internal memories are replaced with models which can be directly contacted by the Instruction Set Simulator. Source: Mentor Graphics echnische Informatik Eingebettete Systeme F 2015, Kap. 4 34

35 HW/SW Co-Verification IV Optimizations Memory accesses are no longer handled by the system simulator. Instead the ISS directly accesses their contents. his reduces the simulation activity faster operation. Source: Mentor Graphics echnische Informatik Eingebettete Systeme F 2015, Kap. 4 35

36 HW/SW Co-Verification V unoptimized ime optimized ime at which optimizations were applied Events & clock cycles reduced Memory access optimized ime at which optimizations were applied Source: Mentor Graphics clock count stays the same but simulation events reduced echnische Informatik Eingebettete Systeme F 2015, Kap. 4 36

37 HW/SW Co-Verification VI Advantages HW/SW integration earlier in design flow. Simulation model acts as virtual hardware. Better communication between hardware and software design teams. Debugging of software starts earlier, hence, more time can be spent developing and debugging the code. Faster design cycles. Software is validated against hardware. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 37

38 HW/SW Co-Verification VII Advantages Embedded software acts as hardware test-bench. Better hardware/software design data integrity. he possibility of hard ASIC or PCB errors is reduced lower design cycles and re-designs. Hardware prototypes avoided: No manufacturing/build defects, improved system observability, controllability. Reduced unobserved parts of system design before tape-out less gray areas lower project risks! echnische Informatik Eingebettete Systeme F 2015, Kap. 4 38

39 Design Schedule Flow with HW/SW co-design und co-verification System Design Hardware Design Prototype Build Hardware Debug Software Design Software Coding System Debug Project Complete Debugging on virtual prototype Earlier project finish echnische Informatik Eingebettete Systeme F 2015, Kap. 4 39

40 ools Mentor Seamless supports a plethora of CPU models integrated with ModelSim CoWare SPW Synopsys CoCentric System Studio SystemC development platform echnische Informatik Eingebettete Systeme F 2015, Kap. 4 40

41 Formal Verification I Simulation is a very crude tool for verification Complex and tedious task, even if really many complex simulations are constructed, they never can explore all possible behaviors. Formal verification needed In contrast to simulation which explores some of possible behaviors, formal verification conducts a exhaustive exploration of all possible behaviors and shows that the design is correct, or if incorrect, presents a counter-example a proof that the design has a failure. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 41

42 Formal Verification II heorem proving Uses axioms, rules to prove system correctness, but there is no guarantee that it will terminate. Is difficult and time consuming. Equivalence checking Checks if two circuits or two different implementations of circuits are equivalent, LVS logic-versus-schematic. Model checking, Assertion Based Verification Automatic technique to prove correctness of systems: digital systems, communication protocols, etc. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 42

43 Binary Decision Diagrams Binary Decision Diagram (BDD) Are a compact data structure for Boolean logic, can represent sets of objects (states) encoded as Boolean functions Reduced ordered BBDs (ROBBD) are a canonical form able to describe Boolean formulas. Equivalent combinational circuits have identical ROBBDs. Construction Remove duplicate terminals Remove duplicate nodes (isomorphic subgraphs) Remove internal nodes with identical children echnische Informatik Eingebettete Systeme F 2015, Kap. 4 43

44 BDD Construction I Construction of a Reduced Ordered BBD a b c f f = a c b c a 1 edge 0 edge b b c c c c Decision ree echnische Informatik Eingebettete Systeme F 2015, Kap. 4 44

45 BBD Construction II 1 edge 0 edge f f = a c b c f a a a b b b b b c c c c c c c Remove duplicate terminals 2. Remove duplicate nodes 3. Remove redundant nodes echnische Informatik Eingebettete Systeme F 2015, Kap. 4 45

46 BDD Application to Verification I Equivalence of combinational circuits Canonicity property of BBDs: if F and G are equivalent, their ROBBDs are identical (for the same ordering of variables) f = a b c a b c a b c g = a c b c a a b b c c echnische Informatik Eingebettete Systeme F 2015, Kap. 4 46

47 BDD Application to Verification II Functional test generation o test for H=1 (0), find a path in the BBD to terminal 1 (0). he path, expressed in function variables, gives a satisfying solution a test vector. b H a a c a b c c 0 1 echnische Informatik Eingebettete Systeme F 2015, Kap. 4 47

48 What Users are Saying System integration time reduced by 2/3. ASIC problems found by software engineers, would have to be solved with a ASIC re-design. he HW/SW interface may be tested from the software point of view. Modifications possible! he complete software could be tested with simulation ROS, drivers, application, interface, A software engineer quoted: All areas which were simulated also worked on the real hardware without changes! echnische Informatik Eingebettete Systeme F 2015, Kap. 4 48

49 Summary We have learned about: what verification is, what HW/SW Coverification is, coming problems with verification complexity, and a short introduction to formal verification. echnische Informatik Eingebettete Systeme F 2015, Kap. 4 49

50 References 1. International echnology Roadmap for Semiconductors (IRS), 2003 Edition, Homepage: requires login 2. Clive Max Maxfield. he Design Warrior s Guide to FPGAs, Elsevier, 2004, ISBN: CoWare s Homepage: 4. Mentor Graphics Homepage: 5. Synopsys Homepage: 6. Cadence Homepage: 7. R.E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE rans. On Computers, C-35(8), pp , Aug echnische Informatik Eingebettete Systeme F 2015, Kap. 4 50