System-on. on-chip Design Flow. Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems.
|
|
- Andrew Porter
- 8 years ago
- Views:
Transcription
1 System-on on-chip Design Flow Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems Jouni Tomberg / TUT 1
2 SoC - How and with whom? SoC Players Markets Flows Bottlenecks IP and platform metrics Jouni Tomberg / TUT 2
3 Definitions Frontend design Design from system level to cell library level netlist Backend design Design from netlist level to Placed & Routed production ready database ASIC flow Netlist handoff to ASIC vendor (takes care of the backend) COT (Customer Owned Tooling) flow P&R database handoff to foundry (takes care of the production) Jouni Tomberg / TUT 3
4 SoC Players IP provider Standard function blocks Customer (end user) IC's Requirement specification Production requirements ASIC vendor or Foundry Netlist or P&R database Design Service provider Physical backannotation Jouni Tomberg / TUT 4
5 Need for System Level Design Jouni Tomberg / TUT 5
6 Market Segments Jouni Tomberg / TUT 6
7 Design Productivity Gap Jouni Tomberg / TUT 7
8 Typical Design Flow Tasks System/ Algorithm Behavioral RTL Gate-level Transistor/ Physical Implement Define System Create/select Algorithms Filter design Protocol Development Create behavioral description Code generation Wordlength optimizatiuon Architectural Tradeoffs Partitioning Create RTL description Behavioral Synthesis Code generation Design Planning Create Netlist Optimize Netlist Logic Synthesis Datapath Synthesis Test Synthesis Power Optimization Retiming Create physical representation Place & Route Clock-tree synthesis Power Routing Transistor Optimization Verify Verify system function Verify Algorithm performance System Simulation HW/SW Coverification Verify behavioral description (function and performance) Simulation Testbench Generation HW/SW Coverifiication Verify RTL description (function and performance) Simulation Power Analysis RTL quality analysis Emulation Verify Netlist (function and performance) Simulation Equivalence Checking Static Timing Analysis Power Analysis Test Analysis/ATPG Verify physical design DRC, LVS Power analysis Rail analysis Static Timing analysis Parasitic Extraction Models/IP System model components System environments Reference Kits Behavioral models RAM Models Part models Bus Models Cores RTL models RAM models Part models Bus Models Cores (functional & timing Models) Gate models Bus Models Synthesis/simulation libraries Physical/transistor models Std Cell libraries Gate Array libraries Jouni Tomberg / TUT 8
9 Design Flows Design Flows Source: T. Moxon / EEDesign, Jouni Tomberg / TUT 9
10 ASIC design flow interfaces DESIGN TEAM CUSTOMER ASIC VENDOR Requirement spec Technical info for quotation ASIC quotation Data sheet for acceptance Library & tools Verification for acceptance (modeler/testbench/simul.results) Netlist, test vectors, arch.plan Backannotation from P&R Acceptance for prototype production (sign off) Prototype ASICs (/risk production) Prototype acceptance Mass production ASICs Jouni Tomberg / TUT 10
11 Importance of Specification Jouni Tomberg / TUT 11
12 Design Bottlenecks * Source EETIMES EDA 2000 Survey Simulation/Design Verification 51% Design Creation Place & Route 32% 32% Post Layout Optimization 26% Parasitic Extraction System or System-on-Chip Layout Versus Schematic(LVS) Design Rule Check (DRC) 17% 17% 17% Static Timing Analysis 16% Synthesis 15% Delay Calculation 13% Base = 545 0% 10% 20% 30% 40% 50% 60% % of project effort devoted to design verification! Jouni Tomberg / TUT 12
13 Verification Importance Jouni Tomberg / TUT 13
14 Project Scheduling External constraints Targeted market entry ASIC vendor Layout generation (P&R) Mask producing Prototype processing Prototype acceptance Volume production starting delay Design constraints Design team experience Design tools / flows, vendor libraries, IP provider quality System specification iterations Design complexity Verification complexity Production test complexity Jouni Tomberg / TUT 14
15 Differencies between SoC and SoPC design flows SoPC is a FPGA technology based user programmable solution P&R and programming done by the user (vs. backend flow in SoC) No delay on prototype production No delay on mass production start No NRE (production start) costs Production tests done by the IC vendor Design resource and time savings in the design flow Quick and cheap modifications On the other hand certain limitations on performance, integration capacity and mass production costs exists compared to SoC Jouni Tomberg / TUT 15
16 Platform Based Design A platform should consist of a basic set of integrated technologies that defines how the system should function. Design platform / Verification platform Generic platform CPU, memory and standard peripheral fucntions Application specific platform Generic platform plus pre-integrated IP blocks for the given application Jouni Tomberg / TUT 16
17 Platform drivers Source: B. Altizer, L. Cooke, and G. Martin / EEDesign Jouni Tomberg / TUT 17
18 Platform Advantages Reduce integration risk by insuring that all IP works together Reduce licensing and contractual negotiation time per project Reduce cost by allowing efficient reuse in multiple designs It is estimated that in the near future each SoC design will consist of 10 to 15 different IP blocks from 6 to 8 IP vendors Suppose 6 to 8 weeks per IP vendor for evaluation, negotiation and integration of IP into the system => with 8 different IP vendors this means 64 weeks of hidden cost Jouni Tomberg / TUT 18
19 IP Market Dynamics Design dynamics (Dataquest 2002) 30% of a designs are composed of reused circuitry 12% of reused circuit is from outside sources => 3.6% of circuitry is from third parties Contractual and legal issues Legal issues remain a huge bottleneck in the IP purchase process rights, responsibility, guarantee, business model VCX trying to address this bottleneck (with standard Ts &Cs) Evaluation of IP Deciding if a core is viable is biggest technical challenge in IP acquisition process. Opportunities in IP evaluation services Perceived instability of vendors.. Most IP vendors are small and vulnerable Partnerships and alliance can help to resolve perceived volatility ty Software replacing hardware Proliferation of processors in ICs Resulting in more functions being implemented in software SW/HW co-design! Jouni Tomberg / TUT 19
20 IP Market Metrics 46%CAGR 75% License Revenue 25% Royalty Revenue Jouni Tomberg / TUT 20
21 Conclusions The main players in the SoC design flow are Design team, IP provider, IC vendor (or Backend team + Foundry) Efficient SoC design flow is based on IP reuse and platform based design The major bottlenecks are in the test and verification area The system level (specification, HW/SW co-design) and layout level links to RTL design play also an important role in a fluent design flow Jouni Tomberg / TUT 21
Architectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
More informationAgenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
More information7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
More informationIntroduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
More informationTesting of Digital System-on- Chip (SoC)
Testing of Digital System-on- Chip (SoC) 1 Outline of the Talk Introduction to system-on-chip (SoC) design Approaches to SoC design SoC test requirements and challenges Core test wrapper P1500 core test
More informationVHDL-Testbench as Executable Specification
VHDL- as Executable Specification Michael Pichler Zentrum für Mikroelektronik Aargau Fachhochschule Aargau, Steinackerstrasse 5, CH-5210 Windisch Web: www.zma.ch - E-mail: m.pichler@zma.ch Seite 1 Overview
More informationCodesign: The World Of Practice
Codesign: The World Of Practice D. Sreenivasa Rao Senior Manager, System Level Integration Group Analog Devices Inc. May 2007 Analog Devices Inc. ADI is focused on high-end signal processing chips and
More informationDigitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation
More informationCustom design services
Custom design services Your partner for electronic design services and solutions Barco Silex, Barco s center of competence for micro-electronic design, has established a solid reputation in the development
More informationState-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop
Photos placed in horizontal position with even amount of white space between photos and header State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop Michael Holmes Manager, Mixed Signal ASIC/SoC
More informationSystems on Chip Design
Systems on Chip Design College: Engineering Department: Electrical First: Course Definition, a Summary: 1 Course Code: EE 19 Units: 3 credit hrs 3 Level: 3 rd 4 Prerequisite: Basic knowledge of microprocessor/microcontroller
More informationWhat is a System on a Chip?
What is a System on a Chip? Integration of a complete system, that until recently consisted of multiple ICs, onto a single IC. CPU PCI DSP SRAM ROM MPEG SoC DRAM System Chips Why? Characteristics: Complex
More informationEEM870 Embedded System and Experiment Lecture 1: SoC Design Overview
EEM870 Embedded System and Experiment Lecture 1: SoC Design Overview Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw Feb. 2013 Course Overview
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationElectronic system-level development: Finding the right mix of solutions for the right mix of engineers.
Electronic system-level development: Finding the right mix of solutions for the right mix of engineers. Nowadays, System Engineers are placed in the centre of two antagonist flows: microelectronic systems
More informationRapid System Prototyping with FPGAs
Rapid System Prototyping with FPGAs By R.C. Coferand Benjamin F. Harding AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Newnes is an imprint of
More informationAims and Objectives. E 3.05 Digital System Design. Course Syllabus. Course Syllabus (1) Programmable Logic
Aims and Objectives E 3.05 Digital System Design Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk How to go
More informationPlatform-Based Design and the First Generation Dilemma Jiang Xu and Wayne Wolf
Platform-Based Design and the First Generation Dilemma Jiang Xu and Wayne Wolf Dept. of ELE, Princeton University Jiangxu, Wolf@ee.Princeton.edu Abstract In this paper, we analyze system-level design methodologies
More informationon-chip and Embedded Software Perspectives and Needs
Systems-on on-chip and Embedded Software - Perspectives and Needs Miguel Santana Central R&D, STMicroelectronics STMicroelectronics Outline Current trends for SoCs Consequences and challenges Needs: Tackling
More informationSystem-on-Chip Design with Virtual Components
FEATURE ARTICLE Thomas Anderson System-on-Chip Design with Virtual Components Here in the Recycling Age, designing for reuse may sound like a great idea. But with increasing requirements and chip sizes,
More informationHigh-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
More informationShanghai R&D Vacancies August 2014 PV, PE, Intern
RD Shanghai R&D Vacancies August 2014 PV, PE, Intern 1. Lead Software Engineer- Routing (Req#: 9528) Responsible for development and maintenance of signal routing in EDI platform (NanoRoute). Implementation
More informationEEC 119B Spring 2014 Final Project: System-On-Chip Module
EEC 119B Spring 2014 Final Project: System-On-Chip Module Dept. of Electrical and Computer Engineering University of California, Davis Issued: March 14, 2014 Subject to Revision Final Report Due: June
More informationExample-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic
Example-driven Interconnect Synthesis for Heterogeneous Coarse-Grain Reconfigurable Logic Clifford Wolf, Johann Glaser, Florian Schupfer, Jan Haase, Christoph Grimm Computer Technology /99 Overview Ultra-Low-Power
More informationESE566 REPORT3. Design Methodologies for Core-based System-on-Chip HUA TANG OVIDIU CARNU
ESE566 REPORT3 Design Methodologies for Core-based System-on-Chip HUA TANG OVIDIU CARNU Nov 19th, 2002 ABSTRACT: In this report, we discuss several recent published papers on design methodologies of core-based
More informationImplementation Details
LEON3-FT Processor System Scan-I/F FT FT Add-on Add-on 2 2 kbyte kbyte I- I- Cache Cache Scan Scan Test Test UART UART 0 0 UART UART 1 1 Serial 0 Serial 1 EJTAG LEON_3FT LEON_3FT Core Core 8 Reg. Windows
More informationIntroduction to System-on-Chip
Introduction to System-on-Chip COE838: Systems-on-Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
More informationComputer Engineering: Incoming MS Student Orientation Requirements & Course Overview
Computer Engineering: Incoming MS Student Orientation Requirements & Course Overview Prof. Charles Zukowski (caz@columbia.edu) Interim Chair, September 3, 2015 MS Requirements: Overview (see bulletin for
More informationWhite Paper 40-nm FPGAs and the Defense Electronic Design Organization
White Paper 40-nm FPGAs and the Defense Electronic Design Organization Introduction With Altera s introduction of 40-nm FPGAs, the design domains of military electronics that can be addressed with programmable
More informationDefining Platform-Based Design. System Definition. Platform Based Design What is it? Platform-Based Design Definitions: Three Perspectives
Based Design What is it? Question: How many definitions of Based Design are there? Defining -Based Design Answer: How many people to you ask? What does the confusion mean? It is a definition in transition
More informationBest Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
More informationDigital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
More informationDesigning a System-on-Chip (SoC) with an ARM Cortex -M Processor
Designing a System-on-Chip (SoC) with an ARM Cortex -M Processor A Starter Guide Joseph Yiu November 2014 version 1.02 27 Nov 2014 1 - Background Since the ARM Cortex -M0 Processor was released a few years
More informationSpace product assurance
ECSS-Q-ST-60-02C Space product assurance ASIC and FPGA development ECSS Secretariat ESA-ESTEC Requirements & Standards Division Noordwijk, The Netherlands Foreword This Standard is one of the series of
More informationContents. System Development Models and Methods. Design Abstraction and Views. Synthesis. Control/Data-Flow Models. System Synthesis Models
System Development Models and Methods Dipl.-Inf. Mirko Caspar Version: 10.02.L.r-1.0-100929 Contents HW/SW Codesign Process Design Abstraction and Views Synthesis Control/Data-Flow Models System Synthesis
More informationConcept Engineering Adds JavaScript-based Web Capabilities to Nlview at DAC 2016
KAL - Large IP Cores: Memory Controllers: SD/SDIO 2.0/3.0 Controller SDRAM Controller DDR/DDR2/DDR3 SDRAM Controller NAND Flash Controller Flash/EEPROM/SRAM Controller Dear , Concept Engineering
More informationDesign-Kits, Libraries & IPs
Design-Kits, Libraries & IPs Supported CAD tools Design-kits overview Digital, Analog, and RF Libraries IPs Supported CAD tools Design-kits overview ST 65nm Tanner PDK Standard cell Libraries IPs austriamicrosystems
More informationESP-CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation
Datasheet -CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation Overview -CV is an equivalence checker for full custom designs. It enables efficient comparison of a reference design
More informationEingebettete Systeme. 4: Entwurfsmethodik, HW/SW Co-Design. Technische Informatik T T T
Eingebettete Systeme 4: Entwurfsmethodik, HW/SW Co-Design echnische Informatik System Level Design: ools and Flow Refinement of HW/SW Systems ools for HW/SW Co-Design C-based design of HW/SW Systems echnische
More informationIL2225 Physical Design
IL2225 Physical Design Nasim Farahini farahini@kth.se Outline Physical Implementation Styles ASIC physical design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification
More informationFPGA Prototyping Primer
FPGA Prototyping Primer S2C Inc. 1735 Technology Drive, Suite 620 San Jose, CA 95110, USA Tel: +1 408 213 8818 Fax: +1 408 213 8821 www.s2cinc.com What is FPGA prototyping? FPGA prototyping is the methodology
More informationARM Cortex-A9 MPCore Multicore Processor Hierarchical Implementation with IC Compiler
ARM Cortex-A9 MPCore Multicore Processor Hierarchical Implementation with IC Compiler DAC 2008 Philip Watson Philip Watson Implementation Environment Program Manager ARM Ltd Background - Who Are We? Processor
More informationSystem on Chip Design. Michael Nydegger
Short Questions, 26. February 2015 What is meant by the term n-well process? What does this mean for the n-type MOSFETs in your design? What is the meaning of the threshold voltage (practically)? What
More informationLesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
More informationIntroduction to Functional Verification. Niels Burkhardt
Introduction to Functional Verification Overview Verification issues Verification technologies Verification approaches Universal Verification Methodology Conclusion Functional Verification issues Hardware
More informationSemiconductor design Outsourcing: Global trends and Indian perspective. Vasudevan A Date: Aug 29, 2003
Semiconductor design Outsourcing: Global trends and Indian perspective Vasudevan A Date: Aug 29, 2003 Role of Semiconductors in Products Source: IC Insights Semiconductor content in end product increasing
More informationReconfigurable Architecture Requirements for Co-Designed Virtual Machines
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Kenneth B. Kent University of New Brunswick Faculty of Computer Science Fredericton, New Brunswick, Canada ken@unb.ca Micaela Serra
More informationBY STEVE BROWN, CADENCE DESIGN SYSTEMS AND MICHEL GENARD, VIRTUTECH
WHITE PAPER METRIC-DRIVEN VERIFICATION ENSURES SOFTWARE DEVELOPMENT QUALITY BY STEVE BROWN, CADENCE DESIGN SYSTEMS AND MICHEL GENARD, VIRTUTECH INTRODUCTION The complexity of electronic systems is rapidly
More informationA Mixed-Signal System-on-Chip Audio Decoder Design for Education
A Mixed-Signal System-on-Chip Audio Decoder Design for Education R. Koenig, A. Thomas, M. Kuehnle, J. Becker, E.Crocoll, M. Siegel @itiv.uni-karlsruhe.de @ims.uni-karlsruhe.de
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationEmbedded Vision on FPGAs. 2015 The MathWorks, Inc. 1
Embedded Vision on FPGAs 2015 The MathWorks, Inc. 1 Enhanced Edge Detection in MATLAB Test bench Read Image from File Add noise Frame To Pixel Median Filter Edge Detect Pixel To Frame Video Display Design
More informationHunting Asynchronous CDC Violations in the Wild
Hunting Asynchronous Violations in the Wild Chris Kwok Principal Engineer May 4, 2015 is the #2 Verification Problem Why is a Big Problem: 10 or More Clock Domains are Common Even FPGA Users Are Suffering
More informationdesign Synopsys and LANcity
Synopsys and LANcity LANcity Adopts Design Reuse with DesignWare to Bring Low-Cost, High-Speed Cable TV Modem to Consumer Market What does it take to redesign a commercial product for a highly-competitive
More informationSerial port interface for microcontroller embedded into integrated power meter
Serial port interface for microcontroller embedded into integrated power meter Mr. Borisav Jovanović, Prof. dr. Predrag Petković, Prof. dr. Milunka Damnjanović, Faculty of Electronic Engineering Nis, Serbia
More informationUniversity of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design
University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents
More informationSDN and Streamlining the Plumbing. Nick McKeown Stanford University
SDN and Streamlining the Plumbing Nick McKeown Stanford University What is SDN? (when we clear away all the hype) A network in which the control plane is physically separate from the forwarding plane.
More informationPre-tested System-on-Chip Design. Accelerates PLD Development
Pre-tested System-on-Chip Design Accelerates PLD Development March 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 Pre-tested
More informationElectronic systems prototyping: Tools and methodologies for a better observability.
Electronic systems prototyping: Tools and methodologies for a better observability. In an electronic system development flow, a prototyping phase is very diversely valued by the electronic system engineer
More informationQuality. Stages. Alun D. Jones
Quality - by Design Quality Design Review Stages Alun D. Jones Design Review Stages Design Review 0 (DR0) Pre-order & quotation stage Design Review 1 (DR1) Initial kick-off and preliminary specification
More informationProduct Development Flow Including Model- Based Design and System-Level Functional Verification
Product Development Flow Including Model- Based Design and System-Level Functional Verification 2006 The MathWorks, Inc. Ascension Vizinho-Coutry, avizinho@mathworks.fr Agenda Introduction to Model-Based-Design
More informationCurriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design Department of Electrical and Computer Engineering Overview The VLSI Design program is part of two tracks in the department:
More informationGEDAE TM - A Graphical Programming and Autocode Generation Tool for Signal Processor Applications
GEDAE TM - A Graphical Programming and Autocode Generation Tool for Signal Processor Applications Harris Z. Zebrowitz Lockheed Martin Advanced Technology Laboratories 1 Federal Street Camden, NJ 08102
More informationEmbedded Systems. introduction. Jan Madsen
Embedded Systems introduction Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard Petersens Plads, Building 321 DK2800 Lyngby, Denmark jan@imm.dtu.dk Wireless Sensor
More informationIntroduction to HW/SW Co-Design of Embedded Systems
Introduction to HW/SW Co-Design of Embedded Systems Prof. Cristina SILVANO Politecnico di Milano Dipartimento di Elettronica e Informazione P.za L. Da Vinci 32, I-20133 Milano (Italy) Ph.: +39-02-2399-3692
More informationDEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM
DEVELOPING TRENDS OF SYSTEM ON A CHIP AND EMBEDDED SYSTEM * Monire Norouzi Young Researchers and Elite Club, Shabestar Branch, Islamic Azad University, Shabestar, Iran *Author for Correspondence ABSTRACT
More informationSystem-on-Chip Design Verification: Challenges and State-of-the-art
System-on-Chip Design Verification: Challenges and State-of-the-art Prof. Sofiène Tahar Hardware Verification Group Concordia University Montréal, QC, CANADA MCSOC 12 Aizu-Wakamatsu, Fukushima, Japan September
More informationSeptember 25, 2007. Maya Gokhale Georgia Institute of Technology
NAND Flash Storage for High Performance Computing Craig Ulmer cdulmer@sandia.gov September 25, 2007 Craig Ulmer Maya Gokhale Greg Diamos Michael Rewak SNL/CA, LLNL Georgia Institute of Technology University
More informationModeling a GPS Receiver Using SystemC
Modeling a GPS Receiver using SystemC Modeling a GPS Receiver Using SystemC Bernhard Niemann Reiner Büttner Martin Speitel http://www.iis.fhg.de http://www.iis.fhg.de/kursbuch/kurse/systemc.html The e
More informationKEEP IT SYNPLE STUPID
Utilizing Programmable Logic for Analyzing Hardware Targets Dmitry Nedospasov SHORT DESCRIPTION Hardware security analysis differs from software security analysis primarily in the tools
More informationELEC 5260/6260/6266 Embedded Computing Systems
ELEC 5260/6260/6266 Embedded Computing Systems Spring 2016 Victor P. Nelson Text: Computers as Components, 3 rd Edition Prof. Marilyn Wolf (Georgia Tech) Course Topics Embedded system design & modeling
More informationEmbedded Systems Engineering Certificate Program
Engineering Programs Embedded Systems Engineering Certificate Program Accelerate Your Career extension.uci.edu/embedded University of California, Irvine Extension s professional certificate and specialized
More informationDesign of a High Speed Communications Link Using Field Programmable Gate Arrays
Customer-Authored Application Note AC103 Design of a High Speed Communications Link Using Field Programmable Gate Arrays Amy Lovelace, Technical Staff Engineer Alcatel Network Systems Introduction A communication
More informationOptimizing Configuration and Application Mapping for MPSoC Architectures
Optimizing Configuration and Application Mapping for MPSoC Architectures École Polytechnique de Montréal, Canada Email : Sebastien.Le-Beux@polymtl.ca 1 Multi-Processor Systems on Chip (MPSoC) Design Trends
More informationChapter 13: Verification
Chapter 13: Verification Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010,
More informationIMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR
International Journal of Engineering & Science Research IMPLEMENTATION OF BACKEND SYNTHESIS AND STATIC TIMING ANALYSIS OF PROCESSOR LOCAL BUS(PLB) PERFORMANCE MONITOR ABSTRACT Pathik Gandhi* 1, Milan Dalwadi
More informationAMS Verification at SoC Level: A practical approach for using VAMS vs SPICE views
AMS Verification at SoC Level: A practical approach for using VAMS vs SPICE views Nitin Pant, Gautham Harinarayan, Manmohan Rana Accellera Systems Initiative 1 Agenda Need for SoC AMS Verification Mixed
More informationConcurrent Hardware/Software Development Platforms Speed System Integration and Bring-Up
Concurrent Hardware/Software Development Platforms Speed System Integration and Bring-Up Author: Ran Avinun, Cadence Design Systems, Inc. Hardware/software development platforms such as virtual prototyping,
More informationFPGA-Centric Functional Verification
FPGA-Centric Functional Verification Mark Litterick Senior Consultant, Verilab Ltd. Scotland & Ireland Designers Forum 2002 Presentation Outline Complex FPGA verification problem Propose a practical solution
More informationTesting & Verification of Digital Circuits ECE/CS 5745/6745. Hardware Verification using Symbolic Computation
Testing & Verification of Digital Circuits ECE/CS 5745/6745 Hardware Verification using Symbolic Computation Instructor: Priyank Kalla (kalla@ece.utah.edu) 3 Credits Mon, Wed, 1:25-2:45pm, WEB L105 Office
More informationEli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and
Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Simulink targeting ASIC/FGPA. Previously Worked as logic
More informationDesign Cycle for Microprocessors
Cycle for Microprocessors Raúl Martínez Intel Barcelona Research Center Cursos de Verano 2010 UCLM Intel Corporation, 2010 Agenda Introduction plan Architecture Microarchitecture Logic Silicon ramp Types
More informationARM Webinar series. ARM Based SoC. Abey Thomas
ARM Webinar series ARM Based SoC Verification Abey Thomas Agenda About ARM and ARM IP ARM based SoC Verification challenges Verification planning and strategy IP Connectivity verification Performance verification
More informationSOC architecture and design
SOC architecture and design system-on-chip (SOC) processors: become components in a system SOC covers many topics processor: pipelined, superscalar, VLIW, array, vector storage: cache, embedded and external
More informationNetworking Remote-Controlled Moving Image Monitoring System
Networking Remote-Controlled Moving Image Monitoring System First Prize Networking Remote-Controlled Moving Image Monitoring System Institution: Participants: Instructor: National Chung Hsing University
More informationAsynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton Dept. of Electrical and Computer Engineering University of British Columbia bradq@ece.ubc.ca
More informationFondamenti su strumenti di sviluppo per microcontrollori PIC
Fondamenti su strumenti di sviluppo per microcontrollori PIC MPSIM ICE 2000 ICD 2 REAL ICE PICSTART Ad uso interno del corso Elettronica e Telecomunicazioni 1 2 MPLAB SIM /1 MPLAB SIM is a discrete-event
More informationAssertion Synthesis Enabling Assertion-Based Verification For Simulation, Formal and Emulation Flows
Assertion Synthesis Enabling Assertion-Based Verification For Simulation, Formal and Emulation Flows Manual Assertion Creation is ABV Bottleneck Assertion-Based Verification adopted by leading design companies
More informationUnderstanding DO-254 Compliance for the Verification of Airborne Digital Hardware
White Paper Understanding DO-254 Compliance for the of Airborne Digital Hardware October 2009 Authors Dr. Paul Marriott XtremeEDA Corporation Anthony D. Stone Synopsys, Inc Abstract This whitepaper is
More informationBUILD VERSUS BUY. Understanding the Total Cost of Embedded Design. www.ni.com/buildvsbuy
BUILD VERSUS BUY Understanding the Total Cost of Embedded Design Table of Contents I. Introduction II. The Build Approach: Custom Design a. Hardware Design b. Software Design c. Manufacturing d. System
More informationNIOS II Based Embedded Web Server Development for Networking Applications
NIOS II Based Embedded Web Server Development for Networking Applications 1 Sheetal Bhoyar, 2 Dr. D. V. Padole 1 Research Scholar, G. H. Raisoni College of Engineering, Nagpur, India 2 Professor, G. H.
More informationAllegro Design Authoring
Create design intent with ease for simple to complex designs Systems companies looking to create new products at the lowest possible cost need a way to author their designs with ease in a shorter, more
More informationWhite Paper. S2C Inc. 1735 Technology Drive, Suite 620 San Jose, CA 95110, USA Tel: +1 408 213 8818 Fax: +1 408 213 8821 www.s2cinc.com.
White Paper FPGA Prototyping of System-on-Chip Designs The Need for a Complete Prototyping Platform for Any Design Size, Any Design Stage with Enterprise-Wide Access, Anytime, Anywhere S2C Inc. 1735 Technology
More informationMAJORS: Computer Engineering, Computer Science, Electrical Engineering
Qualcomm MAJORS: Computer Engineering, Computer Science, Electrical Engineering TITLE: Intern - Software Engineer - Summer 2012 JOB DESCRIPTION: G1889814 Job Title Intern - Software Engineer - Summer 2012
More informationHardware/Software Codesign Overview
Hardware/Software Codesign Overview Education & Facilitation Program Module 14 Version 3.00 All rights reserved. This information is copyrighted by the SCRA, through its Advanced Technology Institute,
More informationIngar Fredriksen AVR Applications Manager. Tromsø August 12, 2005
Ingar Fredriksen AVR Applications Manager Tromsø August 12, 2005 Atmel Norway 2005 Atmel Norway 2005 The history of computers Foundation for modern computing 3 An automatic computing machine must have:
More informationDesign Verification and Test of Digital VLSI Circuits NPTEL Video Course. Module-VII Lecture-I Introduction to Digital VLSI Testing
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-VII Lecture-I Introduction to Digital VLSI Testing VLSI Design, Verification and Test Flow Customer's Requirements Specifications
More informationVerification of Triple Modular Redundancy (TMR) Insertion for Reliable and Trusted Systems
Verification of Triple Modular Redundancy (TMR) Insertion for Reliable and Trusted Systems Melanie Berg 1, Kenneth LaBel 2 1.AS&D in support of NASA/GSFC Melanie.D.Berg@NASA.gov 2. NASA/GSFC Kenneth.A.LaBel@NASA.gov
More informationMoving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim?
Moving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim? Successful FPGA datacenter usage at scale will require differentiated capability, programming ease, and scalable implementation models Executive
More informationProgrammable Logic IP Cores in SoC Design: Opportunities and Challenges
Programmable Logic IP Cores in SoC Design: Opportunities and Challenges Steven J.E. Wilton and Resve Saleh Department of Electrical and Computer Engineering University of British Columbia Vancouver, B.C.,
More information1 Introduction. 5 Nontechnical Issues. 6 Summary. c Dr inż. Ignacy Pardyka (Inf.UJK) Systemy wbudowane Rok akad. 2011/2012 2 / 64
Introduction Introduction SSTEM WBUDOWAE Design Methodology c Dr inż. Ignacy Pardyka UIWERSTET JAA KOCHAOWSKIEGO w Kielcach Rok akad. 2/22 2 Synthesis 3 4 Design for Test 5 ontechnical Issues 6 Summary
More information