Extending the Power of FPGAs. Salil Raje, Xilinx
|
|
- Toby Hubbard
- 8 years ago
- Views:
Transcription
1
2 Extending the Power of FPGAs Salil Raje, Xilinx
3 Extending the Power of FPGAs The Journey has Begun Salil Raje Xilinx Corporate Vice President Software and IP Products Development
4 Agenda The Evolution of FPGAs and FPGA Programming IP-Centric Design with High Level Languages Software Defined Systems
5 The Evolution of FPGAs and FPGA Programming
6 The Evolution of Programmable Devices Logic Cells 1M 3D ICs 10K Programmable SoCs FPGAs 100 PLDs
7 The Progression of FPGA Design Methodology Logic Software Defined Cells 1M IP-Centric with High-level Languages 10K Schematics RTL Programmable SoCs 3D ICs FPGAs 100 PLDs
8 The Shift in Developer Personas Application Developer Logic Software Defined Cells 1M Hardware Designer Algorithm Developer Embedded SW Dev IP-Centric with High-level Languages 10K Hardware Designer Schematics RTL Programmable SoCs 3D ICs FPGAs 100 PLDs
9 IP-Centric Design with High Level Languages IP-Centric Design with High Level Languages
10 Step 1: Leverage Hard and Soft IP + Embedded Processors Example of Hard IP: Zynq MPSOC Examples of Complex Soft IP AXI-MM AXI-Lite AXI-MM interconnect AXI-Lite interconnect AXI-MM AXI-MM AXI-Lite VDMA Deinterlacer V Scaler H Scaler CSC Letterboxing AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S router 10x10 AXI4-S OTN Subsystem Video Subsystem HMC Controller Digital Pre-Distortion SmartConnect
11 Step 2: Develop New IP blocks in C/C++ Algorithmic Specification Micro-architecture Exploration RTL Implementation FPGA Integration Create IP from C/C++/System C algorithm specification Abstract algorithm verification 10,000x faster than RTL sim Traditional FPGA design experience not required
12 Step 3: Use Automated IP Assembly = IP Assembly Example: Zynq Processor Subsystem + Video Subsystem + 6 IP Blocks 4700 lines of VHDL (top-level connectivity only) Video Processing IP Subsystem
13 High Level Design Case Study: GainSpeed Venture-backed start-up Products for cable operators to: Meet skyrocketing capacity requirements of streaming video Cost-effectively migrate networks to a software-driven, all-ip architecture Need to be 10x better and 10x cheaper than much larger incumbents Have a much smaller team and need to work smarter 13
14 Previous Approach to Design 100K+ lines of RTL RTL RTL RTL (VHDL) Test Bench Test Test Bench Bench C) C) (System C) Testbench same as driver code Model Sim Minimal Test Cases Synthesis P&R System Debug (Chipscope) Exhaustive Corner Cases Used Virtex-6 240Ts, targeting 200+ MHz Ran P&R on 100 servers Spent 20% of time designing and 80% making it work Took a team of 10 engineers working for 2 years 14
15 Current Design Methodology : HLS + IPI Low 1000s lines of C code RTL IP RTL Blocks (VHDL) (C code)) Test Bench Test Test Bench Bench (System C) C) (C code) C Compiler Exhaustive Test Cases HLS IPI Synthesis Kintex 480T + off-the-shelf parts Used HLS to build 80% of the IP Blocks DSP functions, closed-loop timing recovery, DMA engines, etc Fast functional simulation in C P&R Much better coverage achieved earlier Team of 2 people working for 6 months System Debug (Chipscope) System-level Debug 15
16 Automated IP Assembly Eliminated grunt-work in wiring IP 16
17 Overall Project Results Elapsed time from project start to running system in lab: 6 months Total number of IP blocks integrated: 30+ Leveraged key IP cores: SRIO, 10G Ethernet MAC, MIG controller, FIR Compiler, Reed-Solomon Design running at 368 MHz in Kintex-7 Enabled co-debug with software developers 17
18 The Era of Software Defined Systems
19 Why FPGAs for Software Defined Systems? The Era of Virtualization Reconfigurable computing, storage and networking in the cloud The Thirst for Acceleration Heterogeneous computing Compute-intensive algorithms DNA sequencing Search engines Video processing Encryption/Decryption Packet routing FPGAs and Programmable SoCs: Power-efficient Reconfigurable Massively-Parallel Compute Engines
20 Query Example of FPGAs as Accelerators Smith-Waterman DNA Sequencing Application Reference Compares Query(N) with Reference(M) genome strings Involves MxN Matrix Computation and Dynamic Programming Maximal parallelism along diagonals Xilinx Virtex-7 690T (reference) Intel Xeon E core Ratio Virtex-7 vs Intel 12 core Intel Xeon Phi 5110P 60 core Ratio Virtex-7 vs Intel 60 Core GCUPS Watts GCUPS/Watt
21 SDSoc: Software Defined SoC Development Applications: Machine Vision Driver Assistance/ADAS Software-Defined Radio (SDR) Wireless Radio Surveillance UAV / Drones Full System Optimizing Compiler ARM Code Main( ) C/C++ Development System-level Profiling Mark C/C++ Functions for Acceleration GCC Connectivity HLS+ SP&R Standard Eclipse IDE Accelerator Func( ) Embedded ARM Processor Subsystem Programmable Logic
22 SDAccel: Software Defined Algorithm Acceleration Sample Applications: Machine Learning Bioinformatics Graph Processing Stringology Data Analytics Modelling Science Codes Signal Processing Video & Image Processing Software-Defined FPGA Acceleration
23 Platforms Enable Software Defined FPGA Systems Pre-defined Platform Hardware System Performance Partial Design Board Algorithms Support Reconfig Analysis & Host Software Stack
24 Summary HW designers: SW developers: C-based IP development + highlevel IP assembly are the next step beyond RTL Software-defined algorithm development + platforms will enable you to exploit the power of FPGAs & SoCs We re making major investments in next generation silicon and tools that will revolutionize FPGA design
25 Thank You Thank You!
Seeking Opportunities for Hardware Acceleration in Big Data Analytics
Seeking Opportunities for Hardware Acceleration in Big Data Analytics Paul Chow High-Performance Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Toronto Who
More informationHigh-Level Synthesis for FPGA Designs
High-Level Synthesis for FPGA Designs BRINGING BRINGING YOU YOU THE THE NEXT NEXT LEVEL LEVEL IN IN EMBEDDED EMBEDDED DEVELOPMENT DEVELOPMENT Frank de Bont Trainer consultant Cereslaan 10b 5384 VT Heesch
More informationEli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and
Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Simulink targeting ASIC/FGPA. Previously Worked as logic
More information7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
More informationLogiCORE IP AXI Performance Monitor v2.00.a
LogiCORE IP AXI Performance Monitor v2.00.a Product Guide Table of Contents IP Facts Chapter 1: Overview Target Technology................................................................. 9 Applications......................................................................
More informationAgenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
More informationFPGA Accelerator Virtualization in an OpenPOWER cloud. Fei Chen, Yonghua Lin IBM China Research Lab
FPGA Accelerator Virtualization in an OpenPOWER cloud Fei Chen, Yonghua Lin IBM China Research Lab Trend of Acceleration Technology Acceleration in Cloud is Taking Off Used FPGA to accelerate Bing search
More informationProduct Development Flow Including Model- Based Design and System-Level Functional Verification
Product Development Flow Including Model- Based Design and System-Level Functional Verification 2006 The MathWorks, Inc. Ascension Vizinho-Coutry, avizinho@mathworks.fr Agenda Introduction to Model-Based-Design
More information9 REASONS WHY THE VIVADO DESIGN SUITE ACCELERATES DESIGN PRODUCTIVITY
9 REASONS WHY THE VIVADO DESIGN SUITE ACCELERATES DESIGN PRODUCTIVITY Does your development team need to create complex, competitive, next-generation systems in a hurry? Xilinx All Programmable devices
More informationData Center and Cloud Computing Market Landscape and Challenges
Data Center and Cloud Computing Market Landscape and Challenges Manoj Roge, Director Wired & Data Center Solutions Xilinx Inc. #OpenPOWERSummit 1 Outline Data Center Trends Technology Challenges Solution
More informationModel-based system-on-chip design on Altera and Xilinx platforms
CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT Model-based system-on-chip design on Altera and Xilinx platforms Ronald Grootelaar, System Architect RJA.Grootelaar@3t.nl Agenda 3T Company profile Technology
More informationRapid System Prototyping with FPGAs
Rapid System Prototyping with FPGAs By R.C. Coferand Benjamin F. Harding AMSTERDAM BOSTON HEIDELBERG LONDON NEW YORK OXFORD PARIS SAN DIEGO SAN FRANCISCO SINGAPORE SYDNEY TOKYO Newnes is an imprint of
More informationDigitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de NIOS II 1 1 What is Nios II? Altera s Second Generation
More informationZynq-7000 Platform Software Development Using the ARM DS-5 Toolchain Authors: Simon George and Prushothaman Palanichamy
Application Note: Zynq-7000 All Programmable Soc XAPP1185 (v2.0) May 6, 2014 Zynq-7000 Platform Software Development Using the ARM DS-5 Toolchain Authors: Simon George and Prushothaman Palanichamy Summary
More informationCodesign: The World Of Practice
Codesign: The World Of Practice D. Sreenivasa Rao Senior Manager, System Level Integration Group Analog Devices Inc. May 2007 Analog Devices Inc. ADI is focused on high-end signal processing chips and
More information2015 Investor and Analyst Day
2015 Investor and Analyst Day Forward-Looking Statements During the course of this presentation, we may provide projections or other forward-looking statements regarding future events and/or future financial
More informationFPGAs in Next Generation Wireless Networks
FPGAs in Next Generation Wireless Networks March 2010 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com 1 FPGAs in Next Generation
More informationJonathan C. Sevy. Software and Systems Engineering Experience
Jonathan C. Sevy jsevy@cs.drexel.edu http://gicl.cs.drexel.edu/people/sevy Software and Systems Engineering Experience Experienced in all phases of software development, including requirements, architecture
More informationEchtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur
Echtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur 2015 The MathWorks, Inc. 1 Model-Based Design Continuous Verification and Validation Requirements
More informationXeon+FPGA Platform for the Data Center
Xeon+FPGA Platform for the Data Center ISCA/CARL 2015 PK Gupta, Director of Cloud Platform Technology, DCG/CPG Overview Data Center and Workloads Xeon+FPGA Accelerator Platform Applications and Eco-system
More informationArchitectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
More informationReCoSoC'11 Montpellier, France. Implementation Scenario for Teaching Partial Reconfiguration of FPGA
ReCoSoC'11 Montpellier, France Implementation Scenario for Teaching Partial Reconfiguration of FPGA Pierre Leray, Amor Nafkha, Christophe Moy SUPELEC/IETR 22 June 2011 SUPELEC - Campus de Rennes - France
More informationNetworking Virtualization Using FPGAs
Networking Virtualization Using FPGAs Russell Tessier, Deepak Unnikrishnan, Dong Yin, and Lixin Gao Reconfigurable Computing Group Department of Electrical and Computer Engineering University of Massachusetts,
More informationSystem Performance Analysis of an All Programmable SoC
XAPP1219 (v1.1) November 5, 2015 Application Note: Zynq-7000 AP SoC System Performance Analysis of an All Programmable SoC Author: Forrest Pickett Summary This application note educates users on the evaluation,
More informationOptimizing Configuration and Application Mapping for MPSoC Architectures
Optimizing Configuration and Application Mapping for MPSoC Architectures École Polytechnique de Montréal, Canada Email : Sebastien.Le-Beux@polymtl.ca 1 Multi-Processor Systems on Chip (MPSoC) Design Trends
More informationDigital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
More informationDeveloping reliable Multi-Core Embedded-Systems with NI Linux Real-Time
Developing reliable Multi-Core Embedded-Systems with NI Linux Real-Time Oliver Bruder National Instruments Switzerland oliver.bruder@ Embedded Product Design Surveys 66% Product designs complete over budget
More informationNetwork connectivity controllers
Network connectivity controllers High performance connectivity solutions Factory Automation The hostile environment of many factories can have a significant impact on the life expectancy of PCs, and industrially
More informationHigh Performance or Cycle Accuracy?
CHIP DESIGN High Performance or Cycle Accuracy? You can have both! Bill Neifert, Carbon Design Systems Rob Kaye, ARM ATC-100 AGENDA Modelling 101 & Programmer s View (PV) Models Cycle Accurate Models Bringing
More informationCFD Implementation with In-Socket FPGA Accelerators
CFD Implementation with In-Socket FPGA Accelerators Ivan Gonzalez UAM Team at DOVRES FuSim-E Programme Symposium: CFD on Future Architectures C 2 A 2 S 2 E DLR Braunschweig 14 th -15 th October 2009 Outline
More informationVon der Hardware zur Software in FPGAs mit Embedded Prozessoren. Alexander Hahn Senior Field Application Engineer Lattice Semiconductor
Von der Hardware zur Software in FPGAs mit Embedded Prozessoren Alexander Hahn Senior Field Application Engineer Lattice Semiconductor AGENDA Overview Mico32 Embedded Processor Development Tool Chain HW/SW
More informationBest Practises for LabVIEW FPGA Design Flow. uk.ni.com ireland.ni.com
Best Practises for LabVIEW FPGA Design Flow 1 Agenda Overall Application Design Flow Host, Real-Time and FPGA LabVIEW FPGA Architecture Development FPGA Design Flow Common FPGA Architectures Testing and
More informationAXI Performance Monitor v5.0
AXI Performance Monitor v5.0 LogiCORE IP Product Guide Vivado Design Suite Table of Contents IP Facts Chapter 1: Overview Advanced Mode...................................................................
More informationWhy 25GE is the Best Choice for Data Centers
Why 25GE is the Best Choice for Data Centers Gilles Garcia Xilinx Director Wired Communication Business Santa Clara, CA USA April 2015 1 Outline - update Data center drivers Why 25GE The need for 25GE
More informationMAJORS: Computer Engineering, Computer Science, Electrical Engineering
Qualcomm MAJORS: Computer Engineering, Computer Science, Electrical Engineering TITLE: Intern - Software Engineer - Summer 2012 JOB DESCRIPTION: G1889814 Job Title Intern - Software Engineer - Summer 2012
More informationXilinx Training Course Listing
Xilinx Training Course Listing Effective April 1, 2015 II TABLE OF CONTENTS Overview...1 Xilinx Training Course Listing...2 Core Design Skills......3 Product Training......4 Specialty Design Skills...6
More informationWhite Paper 40-nm FPGAs and the Defense Electronic Design Organization
White Paper 40-nm FPGAs and the Defense Electronic Design Organization Introduction With Altera s introduction of 40-nm FPGAs, the design domains of military electronics that can be addressed with programmable
More informationDefining Platform-Based Design. System Definition. Platform Based Design What is it? Platform-Based Design Definitions: Three Perspectives
Based Design What is it? Question: How many definitions of Based Design are there? Defining -Based Design Answer: How many people to you ask? What does the confusion mean? It is a definition in transition
More informationQuartus II Software Design Series : Foundation. Digitale Signalverarbeitung mit FPGA. Digitale Signalverarbeitung mit FPGA (DSF) Quartus II 1
(DSF) Quartus II Stand: Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de jens_onno.krah@fh-koeln.de Quartus II 1 Quartus II Software Design Series : Foundation 2007 Altera
More informationReconfigurable Architecture Requirements for Co-Designed Virtual Machines
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines Kenneth B. Kent University of New Brunswick Faculty of Computer Science Fredericton, New Brunswick, Canada ken@unb.ca Micaela Serra
More informationBuilding an Embedded Processor System on a Xilinx Zync FPGA (Profiling): A Tutorial
Building an Embedded Processor System on a Xilinx Zync FPGA (Profiling): A Tutorial Embedded Processor Hardware Design January 29 th 2015. VIVADO TUTORIAL 1 Table of Contents Requirements... 3 Part 1:
More informationWhite Paper. S2C Inc. 1735 Technology Drive, Suite 620 San Jose, CA 95110, USA Tel: +1 408 213 8818 Fax: +1 408 213 8821 www.s2cinc.com.
White Paper FPGA Prototyping of System-on-Chip Designs The Need for a Complete Prototyping Platform for Any Design Size, Any Design Stage with Enterprise-Wide Access, Anytime, Anywhere S2C Inc. 1735 Technology
More informationPing Pong Game with Touch-screen. March 2012
Ping Pong Game with Touch-screen March 2012 xz2266 Xiang Zhou hz2256 Hao Zheng rz2228 Ran Zheng yc2704 Younggyun Cho Abstract: This project is conducted using the Altera DE2 development board. We are aiming
More informationAny Media Over Any Network. July 14 th, 2015
Any Media Over Any Network July 14 th, 2015 The Megatrend: Any Media Over Any Network AGENDA Solutions for Any Media Over Any Network Strategic Partner of Choice for Broadcast and Pro A/V Page 2 The Megatrend:
More informationMPSoC Designs: Driving Memory and Storage Management IP to Critical Importance
MPSoC Designs: Driving Storage Management IP to Critical Importance Design IP has become an essential part of SoC realization it is a powerful resource multiplier that allows SoC design teams to focus
More informationFloat to Fix conversion
www.thalesgroup.com Float to Fix conversion Fabrice Lemonnier Research & Technology 2 / Thales Research & Technology : Research center of Thales Objective: to propose technological breakthrough for the
More informationOpen Flow Controller and Switch Datasheet
Open Flow Controller and Switch Datasheet California State University Chico Alan Braithwaite Spring 2013 Block Diagram Figure 1. High Level Block Diagram The project will consist of a network development
More informationSoftware-Programmable FPGA IoT Platform. Kam Chuen Mak (Lattice Semiconductor) Andrew Canis (LegUp Computing) July 13, 2016
Software-Programmable FPGA IoT Platform Kam Chuen Mak (Lattice Semiconductor) Andrew Canis (LegUp Computing) July 13, 2016 Agenda Introduction Who we are IoT Platform in FPGA Lattice s IoT Vision IoT Platform
More informationHybrid Platform Application in Software Debug
Hybrid Platform Application in Software Debug Jiao Feng July 15 2015.7.15 Software costs in SoC development 2 Early software adoption Previous Development Process IC Development RTL Design Physical Design
More informationOpenSoC Fabric: On-Chip Network Generator
OpenSoC Fabric: On-Chip Network Generator Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf MODSIM 2014 Presentation
More informationAll Programmable Logic. Hans-Joachim Gelke Institute of Embedded Systems. Zürcher Fachhochschule
All Programmable Logic Hans-Joachim Gelke Institute of Embedded Systems Institute of Embedded Systems 31 Assistants 10 Professors 7 Technical Employees 2 Secretaries www.ines.zhaw.ch Research: Education:
More informationBeschleunigen von Algorithmen mit High-Level Synthese auf Xilinx Zynq
08. Oktober 2014 Beschleunigen von Algorithmen mit High-Level Synthese auf Xilinx Zynq Florian Hagel, Missing Link Electronics GmbH We are Our Mission is Our Expertise is a Silicon Valley based technology
More informationFPGA Acceleration using OpenCL & PCIe Accelerators MEW 25
FPGA Acceleration using OpenCL & PCIe Accelerators MEW 25 December 2014 FPGAs in the news» Catapult» Accelerate BING» 2x search acceleration:» ½ the number of servers»
More informationVirtual Platforms Addressing challenges in telecom product development
white paper Virtual Platforms Addressing challenges in telecom product development This page is intentionally left blank. EXECUTIVE SUMMARY Telecom Equipment Manufacturers (TEMs) are currently facing numerous
More information9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
More informationEmbedded Development Tools
Embedded Development Tools Software Development Tools by ARM ARM tools enable developers to get the best from their ARM technology-based systems. Whether implementing an ARM processor-based SoC, writing
More informationFive Ways to Build Flexibility into Industrial Applications with FPGAs
Five Ways to Build Flexibility into Industrial Applications with FPGAs by Jason Chiang and Stefano Zammattio, Altera Corporation WP-01154-2.0 White Paper This document describes using an Altera industrial-grade
More informationRAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition
RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition A Tutorial Approach James O. Hamblen Georgia Institute of Technology Michael D. Furman Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS Boston
More informationIntel Xeon +FPGA Platform for the Data Center
Intel Xeon +FPGA Platform for the Data Center FPL 15 Workshop on Reconfigurable Computing for the Masses PK Gupta, Director of Cloud Platform Technology, DCG/CPG Overview Data Center and Workloads Xeon+FPGA
More informationCompiling PCRE to FPGA for Accelerating SNORT IDS
Compiling PCRE to FPGA for Accelerating SNORT IDS Abhishek Mitra Walid Najjar Laxmi N Bhuyan QuickTime and a QuickTime and a decompressor decompressor are needed to see this picture. are needed to see
More informationUsing Vivado Design Suite with Version Control Systems Author: Jim Wu
Application Note: Vivado Design Suite XAPP1165 (v1.0) August 5, 2013 Using Vivado Design Suite with Version Control Systems Author: Jim Wu Summary This application note provides recommendations for using
More informationIntroduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
More informationBY STEVE BROWN, CADENCE DESIGN SYSTEMS AND MICHEL GENARD, VIRTUTECH
WHITE PAPER METRIC-DRIVEN VERIFICATION ENSURES SOFTWARE DEVELOPMENT QUALITY BY STEVE BROWN, CADENCE DESIGN SYSTEMS AND MICHEL GENARD, VIRTUTECH INTRODUCTION The complexity of electronic systems is rapidly
More informationIntroduction to Functional Verification. Niels Burkhardt
Introduction to Functional Verification Overview Verification issues Verification technologies Verification approaches Universal Verification Methodology Conclusion Functional Verification issues Hardware
More informationCustom design services
Custom design services Your partner for electronic design services and solutions Barco Silex, Barco s center of competence for micro-electronic design, has established a solid reputation in the development
More informationHARNESS project: Managing Heterogeneous Compute Resources for a Cloud Platform
HARNESS project: Managing Heterogeneous Compute Resources for a Cloud Platform J. G. F. Coutinho 1, O. Pell 2, E. O Neill 3, P. Sanders 2, J. McGlone 3, P. Grigoras 1, W. Luk 1, and C. Ragusa 2 1 Imperial
More informationH MICRO CASE STUDY. Device API + IPC mechanism. Electrical and Functional characterization of HMicro s ECG patch
H MICRO CASE STUDY HMicro HMicro is a wireless healthcare chip company to enable industry s first fully disposable wireless patches with high reliability, high data integrity, low cost, small form factor
More informationWhat is a System on a Chip?
What is a System on a Chip? Integration of a complete system, that until recently consisted of multiple ICs, onto a single IC. CPU PCI DSP SRAM ROM MPEG SoC DRAM System Chips Why? Characteristics: Complex
More informationAcceleration for Personalized Medicine Big Data Applications
Acceleration for Personalized Medicine Big Data Applications Zaid Al-Ars Computer Engineering (CE) Lab Delft Data Science Delft University of Technology 1" Introduction Definition & relevance Personalized
More informationGoing to the wire: The next generation financial risk management platform
Going to the wire: The next generation financial risk management platform Ari Studnitzer, MD of Platform Development, CME Group Oskar Mencer, CEO and Founder, Maxeler CME Group CME Group is the world s
More informationSystolic Computing. Fundamentals
Systolic Computing Fundamentals Motivations for Systolic Processing PARALLEL ALGORITHMS WHICH MODEL OF COMPUTATION IS THE BETTER TO USE? HOW MUCH TIME WE EXPECT TO SAVE USING A PARALLEL ALGORITHM? HOW
More informationFPGA Prototyping Primer
FPGA Prototyping Primer S2C Inc. 1735 Technology Drive, Suite 620 San Jose, CA 95110, USA Tel: +1 408 213 8818 Fax: +1 408 213 8821 www.s2cinc.com What is FPGA prototyping? FPGA prototyping is the methodology
More informationReconfig'09 Cancun, Mexico
Reconfig'09 Cancun, Mexico New OPBHW Interface for Real-Time Partial Reconfiguration of FPGA Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy SUPELEC/IETR 10 December 2009 SUPELEC - Campus de
More informationAccelerate Cloud Computing with the Xilinx Zynq SoC
X C E L L E N C E I N N E W A P P L I C AT I O N S Accelerate Cloud Computing with the Xilinx Zynq SoC A novel reconfigurable hardware accelerator speeds the processing of applications based on the MapReduce
More information10/100/1000Mbps Ethernet MAC with Protocol Acceleration MAC-NET Core with Avalon Interface
1 Introduction Ethernet is available in different speeds (10/100/1000 and 10000Mbps) and provides connectivity to meet a wide range of needs from desktop to switches. MorethanIP IP solutions provide a
More informationNetworking Services Trusted at every level and every phase
Networking Services Trusted at every level and every phase freescale.com/netservices Networking Services Overview Freescale has over 1000 in-house software resources providing networking expertise, software
More informationGetting Started with Embedded System Development using MicroBlaze processor & Spartan-3A FPGAs. MicroBlaze
Getting Started with Embedded System Development using MicroBlaze processor & Spartan-3A FPGAs This tutorial is an introduction to Embedded System development with the MicroBlaze soft processor and low
More informationWiSER: Dynamic Spectrum Access Platform and Infrastructure
WiSER: Dynamic Spectrum Access Platform and Infrastructure I. Seskar, D. Grunwald, K. Le, P. Maddala, D. Sicker, D. Raychaudhuri Rutgers, The State University of New Jersey University of Colorado, Boulder
More informationSimplifying Embedded Hardware and Software Development with Targeted Reference Designs
White Paper: Spartan-6 and Virtex-6 FPGAs WP358 (v1.0) December 8, 2009 Simplifying Embedded Hardware and Software Development with Targeted Reference Designs By: Navanee Sundaramoorthy FPGAs are becoming
More informationThe Internet of Things: Opportunities & Challenges
The Internet of Things: Opportunities & Challenges What is the IoT? Things, people and cloud services getting connected via the Internet to enable new use cases and business models Cloud Services How is
More informationHow To Design An Image Processing System On A Chip
RAPID PROTOTYPING PLATFORM FOR RECONFIGURABLE IMAGE PROCESSING B.Kovář 1, J. Kloub 1, J. Schier 1, A. Heřmánek 1, P. Zemčík 2, A. Herout 2 (1) Institute of Information Theory and Automation Academy of
More informationHow Router Technology Shapes Inter-Cloud Computing Service Architecture for The Future Internet
How Router Technology Shapes Inter-Cloud Computing Service Architecture for The Future Internet Professor Jiann-Liang Chen Friday, September 23, 2011 Wireless Networks and Evolutional Communications Laboratory
More informationConcurrent Hardware/Software Development Platforms Speed System Integration and Bring-Up
Concurrent Hardware/Software Development Platforms Speed System Integration and Bring-Up Author: Ran Avinun, Cadence Design Systems, Inc. Hardware/software development platforms such as virtual prototyping,
More informationLinux. Reverse Debugging. Target Communication Framework. Nexus. Intel Trace Hub GDB. PIL Simulation CONTENTS
Android NEWS 2016 AUTOSAR Linux Windows 10 Reverse ging Target Communication Framework ARM CoreSight Requirements Analysis Nexus Timing Tools Intel Trace Hub GDB Unit Testing PIL Simulation Infineon MCDS
More informationSeven Challenges of Embedded Software Development
Corporate Technology Seven Challenges of Embedded Software Development EC consultation meeting New Platforms addressing mixed criticalities Brussels, Feb. 3, 2012 Urs Gleim Siemens AG Corporate Technology
More informationElectronic system-level development: Finding the right mix of solutions for the right mix of engineers.
Electronic system-level development: Finding the right mix of solutions for the right mix of engineers. Nowadays, System Engineers are placed in the centre of two antagonist flows: microelectronic systems
More informationXilinx SDAccel. A Unified Development Environment for Tomorrow s Data Center. By Loring Wirbel Senior Analyst. November 2014. www.linleygroup.
Xilinx SDAccel A Unified Development Environment for Tomorrow s Data Center By Loring Wirbel Senior Analyst November 2014 www.linleygroup.com Copyright 2014 The Linley Group, Inc. This paper examines Xilinx
More informationLesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education
Lesson 7: SYSTEM-ON ON-CHIP (SoC( SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY 1 VLSI chip Integration of high-level components Possess gate-level sophistication in circuits above that of the counter,
More informationSystems on Chip Design
Systems on Chip Design College: Engineering Department: Electrical First: Course Definition, a Summary: 1 Course Code: EE 19 Units: 3 credit hrs 3 Level: 3 rd 4 Prerequisite: Basic knowledge of microprocessor/microcontroller
More informationFSMD and Gezel. Jan Madsen
FSMD and Gezel Jan Madsen Informatics and Mathematical Modeling Technical University of Denmark Richard Petersens Plads, Building 321 DK2800 Lyngby, Denmark jan@imm.dtu.dk Processors Pentium IV General-purpose
More informationArchitekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen. Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik
Architekturen und Einsatz von FPGAs mit integrierten Prozessor Kernen Hans-Joachim Gelke Institute of Embedded Systems Professur für Mikroelektronik Contents Überblick: Aufbau moderner FPGA Einblick: Eigenschaften
More information1. PUBLISHABLE SUMMARY
1. PUBLISHABLE SUMMARY ICT-eMuCo (www.emuco.eu) is a European project with a total budget of 4.6M which is supported by the European Union under the Seventh Framework Programme (FP7) for research and technological
More informationMoving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim?
Moving Beyond CPUs in the Cloud: Will FPGAs Sink or Swim? Successful FPGA datacenter usage at scale will require differentiated capability, programming ease, and scalable implementation models Executive
More informationMicrowatt to Megawatt - Transforming Edge to Data Centre Insights
Security Level: Public Microwatt to Megawatt - Transforming Edge to Data Centre Insights Steve Langridge steve.langridge@huawei.com May 3, 2015 www.huawei.com Agenda HW Acceleration System thinking Big
More informationAttention. restricted to Avnet s X-Fest program and Avnet employees. Any use
Attention The Content material is contained copyright in by this its presentation original authors, is the property and is used of Avnet by Electronics permission. Marketing. This compendium Use of this
More informationEmbedded Systems Engineering Certificate Program
Engineering Programs Embedded Systems Engineering Certificate Program Accelerate Your Career extension.uci.edu/embedded University of California, Irvine Extension s professional certificate and specialized
More informationEricsson Introduces a Hyperscale Cloud Solution
Ericsson Introduces a Hyperscale Cloud Solution The Ericsson HDS 8000 delivers a complete datacenter and cloud platform based on Intel Rack Scale Architecture Solution Brief Ericsson HDS 8000, part of
More informationCloud-Based Apps Drive the Need for Frequency-Flexible Clock Generators in Converged Data Center Networks
Cloud-Based Apps Drive the Need for Frequency-Flexible Generators in Converged Data Center Networks Introduction By Phil Callahan, Senior Marketing Manager, Timing Products, Silicon Labs Skyrocketing network
More informationAN FPGA FRAMEWORK SUPPORTING SOFTWARE PROGRAMMABLE RECONFIGURATION AND RAPID DEVELOPMENT OF SDR APPLICATIONS
AN FPGA FRAMEWORK SUPPORTING SOFTWARE PROGRAMMABLE RECONFIGURATION AND RAPID DEVELOPMENT OF SDR APPLICATIONS David Rupe (BittWare, Concord, NH, USA; drupe@bittware.com) ABSTRACT The role of FPGAs in Software
More informationEVALUATION OF SCHEDULING AND ALLOCATION ALGORITHMS WHILE MAPPING ASSEMBLY CODE ONTO FPGAS
EVALUATION OF SCHEDULING AND ALLOCATION ALGORITHMS WHILE MAPPING ASSEMBLY CODE ONTO FPGAS ABSTRACT Migration of software from older general purpose embedded processors onto newer mixed hardware/software
More information