VHDL-Testbench as Executable Specification

Transcription

1 VHDL- as Executable Specification Michael Pichler Zentrum für Mikroelektronik Aargau Fachhochschule Aargau, Steinackerstrasse 5, CH-5210 Windisch Web: m.pichler@zma.ch Seite 1

2 Overview Project Information Project Description Project Organization Verification Concept General Aspects Project Specific Seite 2

3 Abbreviations ASIC Application Specific IC Used Colors: BFM DUT FPGA SDF VHDL VHSIC VITAL Bus Function Model Design under Test Field Programmable Gate Array Standard Delay Format VHSIC Hardware Description Language Very High Speed Integrated Circuit VHDL Initiative towards ASIC Libraries zma Ascom or Design or Verification Seite 3

4 Project Context up H8M H2M Frame H8M H2M Ts31 serial Interface Ts0 swidec Port A Port B Ts127 Ts0 Ts1 Ts2 Ts3 Ts124 Ts125 Ts126 Ts127 Ts0 Ts31 Ts0 Seite 4

5 Project Implementation swidec_top swidec Bus Interface Generate Clocks DD Path ASIC Collision Checker 0 0 & & nand_tree DU/DD Registers DU Path io_block Ports and Serial Interface FPGA Fast Prototyping Seite 5

6 Project Team Project Management Design Trainer Layout System Know-how Specification Verification Seite 6

7 Overview Project Information Project Description Project Organization Verification Concept General Aspects Project Specific Seite 7

8 Growing Design Verification Investment Design Complexity Time to Market Seite 8

9 Costs of design errors System Time to fix a bug Block Module Design integration stage Seite 9

10 Three different Architectures Stimuli Generator Classical DUT Output Checker Control Stimuli BFM 1..N DUT Reference models DUT Monitor 1..N Compare Seite 10

11 Verification Environment System Design Renoir Renoir / BestBench Design VHDL Simulator (ModelSim) Results VITAL Netlist, SDF-File Seite 11

12 General Verification Aspects System Design Complexity Stimuli Generator Classical DUT Time to Market Output Checker Control Stimuli BFM 1..N DUT Reference models DUT Monitor 1..N Compare Time to fix a bug Block System Design Renoir Design Module Design integration stage Renoir / BestBench VHDL Simulator (ModelSim) Results VITAL Netlist, SDF-File Seite 12

13 Design Flow (1) DESIGN Specification VERIFICATION Structured Analysis Structured Design Design FPGA Synthesis FPGA Place&Route Seite 13 FPGA Prototype RTL Prelayout Postlayout FPGA Boardlevel Verification

14 Design Flow (2) DESIGN VERIFICATION ASIC Synthesis ASIC Place&Route Seite 14 Re-Design Re-Design ASIC RTL Prelayout Postlayout ASIC Boardlevel Verification

15 80 Testcases Stimuli Generator Classical DUT Output Checker Clock MHz H8M H2M µc-interface Serial Interface Two 16-bit Ports Seite 15

16 Statistics 700 Design RTL Verification Total [h] 600 Design Specification Structured Analysis Test Concept Structured Design Test Design Design Top Sheet Synthesis ATPG ClockTree Synthesis Prelayout Verification Layout Postlayout Verification Vendor Netlist Transfer Verification Engineering Samples Testprogram Documentation Consulting Training Projectmanagement Travel Design Kit Education nicht verrechenbar Seite 16

17 Conclusions First Time Right All requirements were met... One for all simulations More verified features implemented than needed in the first hardware version Project Termination on time and on budget Successful co-operation Ascom is satisfied. Seite 17

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