ESE566 REPORT3. Design Methodologies for Core-based System-on-Chip HUA TANG OVIDIU CARNU

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1 ESE566 REPORT3 Design Methodologies for Core-based System-on-Chip HUA TANG OVIDIU CARNU Nov 19th, 2002

2 ABSTRACT: In this report, we discuss several recent published papers on design methodologies of core-based System-on-Chip. There are some critical issues in SoC design, such as power consumption, hardware cost etc. Each of the methodology tries to address some of these issues. We will detail their ideas and their implementation and compare them with each other.

3 SECTION I: Introduction System-on-Chip design is becoming a trend nowdays It is predicted by ITRS that up to 70% of ASICs (Application Specific Integrated Chip) will be SoCs, which is being proved to be true in the electronic market. SoC designs give advantages compared to traditional board design, but at the same time it creates some serious issues which have to be taken care of. As mentioned in [1] [2] we summarize some important ones here. First, as the design becomes more and more complicated: communication can not be specified at RTL (Register Transfer Level), and this level is not adapted to check communication protocols due to very large time cost; second, SoC usually many processor cores and each core may have its own instruction set to increase the flexibility of the system. However, the code is getting big and complex, which is becoming more important that hardware itself. Software may not be written in Assembly Language as today and more effort has to be spent on this issue; third, complex HW/SW interface are required to implement application specific communication interconnect and they have to be adapted to it according to the type of core. Fourth, as more and more processors are integrated into one single chip, chip area, power consumption, hardware cost becomes very crucial. For example, a high power consumption may not be acceptable for portable wireless devices. State-of-art design methodologies deployed is core based system. In core based design, the designer composed a system of cores and has a high degree of freedom to optimize his/her design according to the related design constraints. In this report, we discuss several papers. [1] is paper on an improved design methodology and design environment for application specific multicore SoC architectures. Component based design follows a bottom-up approach, which has the advantage of allowing designers to explore efficient custom solutions with best performances, thus ensuring high degree of freedom. The component based design approach in [1] uses a specification as a virtual architecture which is described in a SystemC-like model and annotated with a set of configuration parameters. Associated tools were developed with the methodology and will be detailed in this report. [2] tries to address the fourth issue of power consumption using a new HW/SW partitioning approach for core based embedded systems. It stem from the observation that mapping clusters of

4 operations to a core can yield high utilization rate of involved resources and thus to minimize power consumption. This report is organized as follows. Section 2 details the methodologies in the papers. Section 3 compares all the mentioned methodologies and associated tools and finally conclusions will be given in Section 4. SECTION II: Improved design methodologies In this section, we will detail the ideas and implementation of the improved design methodologies in the referred papers [1][2]. [1] is a new component based design approach for multicore SoCs and is mainly intended to improve the design efficiency. [2] is a new HW/SW partitioning approach for core based embedded system design which mainly focus on the minimization of power consumption. Application SW Programming API Standard OS Service SW supported pkg(drivers) Hardware Functions realized SW Specific API Custom OS Drivers Hardware (a)application software stack Figure 1. Software Organization (b)functional software stack In traditional SoC architectures, each kind of embedded processor has its own software organization. The application software is generally organized as a stack of layers on top of the hardware. This is shown in Figure 1a. The lowest layer provides the drivers and upper layers provides OS services and SW application layer is generated by the designer. Top layer is application specific software, which is usually written in Assembly or C. The

5 problem with this kind of software organization is that low level programming is very hard and also, it lacks flexibility and portability which makes it difficult to change the hardware part without a complete redesign [1]. To palliate this problem, [1] proposes a higher level programming approach for dedicated software. The new organization of software is shown in Figure 1b. With the new scheme, both dedicated and application software can be written independently from the hardware implementation, which gives a big advantage. As the author mentioned, an additional benefit is that dedicated software can be independent from hardware/software frontiers on architectures components and OS choices [1]. Accordingly, flexibility is created in the design process without loss of performance. The author favors the use of component based design methodology as it increase the abstraction level and is beneficial for design time reduction for communication refinement. So, the key idea by the author is to use an abstract architecture where communication is separated from the component on the hardware side and from the functions on the software side. In the proposed methodology, system is described as a set of virtual components interconnected via channels. Virtual components are composed of wrappers and internal components. Virtual architecture is described by an extension of SystemC. The methodology will generated automatically the wrappers in order to produce a detailed architecture. The author uses a generic multicore SoC architecture in which processors are connected to communication networks via wrappers. Wrappers actually act as communication bridges. Wrapper is composed of a software part and a hardware part. For software part, wrappers provide the implementation of high level communication primitives used in software module. Software wrapper part can also be added more function if more services are required. For the hardware part, the internal structure of wrapper consists of a processor adapter, a channel adapter and an internal bus. In addition, the author also developed a design environment which can automatically generate wrappers. The complete system design flow is as follows: first, an initial internal model is obtained, which is a virtual architecture. Then, from the virtual architecture, hardware wrapper, software wrapper and co-simulation wrapper are generated. The co-simulation wrapper is used to validate the internal model. Finally, executable co-simulation model can be generated and simulated. This high level component-based design methodology is tested on VDSL application, resulting in a

6 15-fold reduction in design effort and the design is as good as commercial or handcrafted designs [1]. The second paper by Jorg Henkel also discussed a HW/SW partitioning approach methodology with the focus to minimize power consumption. HW/SW partitioning has exists for many years, but it is mainly used to improve system performance or keep low system cost without considering the power consumption. The architecture of a system that this methodology applies to consists of a µp core, a set of standard core and a set of application specific cores. The methodology tries to partition between µp core and application specific cores in order to minimize power consumption. The motivation for the methodology is that during execution of a program, different hardware resources in the core are used, hence with a different utilization rate. In a operation, those circuit units which are not active still consumes power because they continue to switch so that waste power. So, the obvious solution to this could be to deploy additional cores for particular purpose so that only related cores works while all the others do not. But it would be better to shut down individual resources within each core rather than deploying additional cores as core based techniques are used in the design and we should allow the use of this state-of-art design methodology. The input to the partitioning process is a behavior description of an application that is subject to partitioning between ASIC core and µp core. It follows several steps here. Step 1, a graph from the description is derived which represents operations. Step 2, decomposition of the graph into clusters is performed. The implementation of the cluster on an ASIC core might lead to energy reduction. In step 3, the amount of energy that can be saved in that case is calculated. Step 4 performs a pre-selection of clusters which are promising to give power saving. Due to the architecture for the methodology, additional traffic via the bus structure is caused. Next, in step 5 a loop is started for all sets of resources which is designed by the designer. Then, a list schedule is performed on the current cluster to prepare the following step 9, in which the actual utilization rate of the core is calculated and it is tested whether it can achieve energy saving on an ASIC core or a µp core. If the current cluster can achieve energy saving, then step 10 is activated to roughly estimate how much energy can be saved. Energy is calculated by using the previous utilization rate if it is implemented in ASIC core and dedicated instruction set energy simulation tool is

7 used if in a µp core. The whole portioning process is implemented in an optimization algorithm. The objective function includes the normalized energy power consumption and the hardware cost. In the design process, those clusters that yield a higher utilization rate and that yield the highest core of the objective function are provided to the hardware synthesis flow. The methodology was tested on several cases and high energy savings between 35% to 94% were achieved with also a decrease of execution time of 17% to 35%. Meanwhile, the additional hardware cost is reasonable. SECTION IV: Comparison of the methodologies In Section 2, we discussed several design methodologies for the core based embedded system design. We will try to compare them in term of several metrics even though they are targeted to different objectives. Paper in [1] presents a methodology to improve the design cycle of embedded system based on a new organization of the software part. It is a very efficient methodology and can generate as good designs as commercial tools. But power consumption is not reported in the paper. On the other hand, paper [2] focus on minimizing the power consumption of embedded system by a new HW/SW portioning algorithm. High energy savings were reported in the paper with a little bit higher hardware cost. We believe there are two concerns with the methodology: one is that the long execution time of the design process, especially when considering the RTL level simulation to calculate energy saving, the other one is that it is mainly targeted to DSP-oriented applications.

8 SECTION V: Conclusions This report discusses several design methodologies for embedded systems. In [1], a high level component based design methodology and design environment for application specific multicore SoC architectures, resulting in short design cycle. A low power HW/SW partitioning approach was also discussed to minimize power consumption.

9 REFERENCES: [1] W. Cesario et al, "Component-Based Design Approach for Multicore SoCs'', Design Automation Conference,2001. [2] Jorg Henkel et al, "A Low Power Hardware/Software Partitioning Approach for Core-based Embedded Systems", Design Automation Conference, 1999.