Controller Implementation--Part I. Cascading Edge-triggered Flip-Flops

Transcription

1 Controller Implementation--Part I Alternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time state: Divide and Counter Jump counters Microprogramming (ROM) based approaches» branch sequencers» horizontal microcode» vertical microcode CS 50 - Fall 2005 Lec #4: Control Implementation - Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) IN Q0 Q D Q D Q OUT 00 IN Q0 Q CS 50 - Fall 2005 Lec #4: Control Implementation - 2

2 Cascading Edge-triggered Flip-Flops Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) IN Q0 Q D Q D Q OUT Delay Clk 00 IN Q0 Q Clk CS 50 - Fall 2005 Lec #4: Control Implementation - 3 Clock Skew The problem Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay) Effect of skew on cascaded flip-flops: 00 In Q0 Q is a delayed version of original state: IN = 0, Q0 =, Q = due to skew, next state becomes: Q0 = 0, Q = 0, and not Q0 = 0, Q = CS 50 - Fall 2005 Lec #4: Control Implementation - 4

3 Why Gating of Clocks is Bad! LD Reg Reg Clk GOOD Clk LD BAD gatedclk Do NOT Mess With Clock Signals! CS 50 - Fall 2005 Lec #4: Control Implementation - 5 Why Gating of Clocks is Bad! LD generated by FSM shortly after rising edge of Clk LD gatedclk Runt pulse plays HAVOC with register internals! NASTY HACK: delay LD through negative edge triggered FF to ensure that it won t change during next positive edge event Clk LDn gatedclk Clk skew PLUS LD delayed by half clock cycle What is the effect on your register transfers? Do NOT Mess With Clock Signals! CS 50 - Fall 2005 Lec #4: Control Implementation - 6

4 Why Gating of Clocks is Bad! Reset Counter Reg Clk BAD slowclk Do NOT Mess With Clock Signals! CS 50 - Fall 2005 Lec #4: Control Implementation - 7 Why Gating of Clocks is Bad! Reset LD Counter Reg Clk Better! Do NOT Mess With Clock Signals! CS 50 - Fall 2005 Lec #4: Control Implementation - 8

5 Alternative Ways to Implement Processor FSMs "Random Logic" based on Moore and Mealy Design Classical Finite State Machine Design Divide and Conquer Approach: Time-State Method Partition FSM into multiple communicating FSMs Exploit Logic Block Functionality: Jump Counters Counters, Multiplexers, Decoders Microprogramming: ROM-based methods Direct encoding of next states and outputs CS 50 - Fall 2005 Lec #4: Control Implementation - 9 Random Logic Perhaps poor choice of terms for "classical" FSMs Contrast with structured logic: PLA, FPGA, ROM-based (latter used in microprogrammed controllers) Could just as easily construct Moore and Mealy machines with these components CS 50 - Fall 2005 Lec #4: Control Implementation - 0

6 Moore Machine State Diagram RES IF0 Reset 0 PC PC MAR, PC + PC Note capture of MBR in these states IF IF2 MAR Mem, Read/Write, Request, Mem MBR IF3 MBR IR LD0 LD LD2 IR MAR MAR Mem, Read/Write, Request, Mem MBR MBR AC =00 =0 ST0 ST OD IR MAR, AC MBR MAR Mem, 0 Read/Write, Request, MBR Mem =0 AD0 AD AD2 = IR MAR MAR Mem, Read/Write, Request, Mem MBR MBR + AC AC BR0 = BR =0 IR PC CS 50 - Fall 2005 Lec #4: Control Implementation - Memory-Register Interface Timing IF IF2 IF2 IF2 IF3 WAIT Mem Bus Data Valid Latch MBR Invalid Data Latched Invalid Data Latched Valid Data Latched Valid data latched on IF2 to IF3 transition because data must be valid before Wait can go low CS 50 - Fall 2005 Lec #4: Control Implementation - 2

7 Moore Machine Diagram Reset Wait IR<5> IR<4> AC<5> Clock Next State Logic State 6 states, 4 bit state register Next State Logic: 9 Inputs, 4 Outputs Output Logic: 4 Inputs, 8 Outputs Output Logic Read/Write Request 0 PC PC + PC PC ABUS IR ABUS ABUS MAR ABUS PC MAR Memory Address Bus Memory Data Bus MBR MBR Memory Data Bus MBR MBUS MBUS IR MBUS ALU B MBUS AC RBUS AC RBUS MBR ALU ADD These can be implemented via ROM or PAL/PLA Next State: 52 x 4 bit ROM Output: 6 x 8 bit ROM CS 50 - Fall 2005 Lec #4: Control Implementation - 3 Moore Machine State Table ResetWaitIR<5> IR<4> AC<5>Current State Next State Register Transfer Ops X X X X X RES (0000) 0 X X X X RES (0000) IF0 (000) 0 PC 0 X X X X IF0 (000) IF (000) PC MAR, PC + PC 0 0 X X X IF (000) IF (000) 0 X X X IF (000) IF2 (00) 0 X X X IF2 (00) IF2 (00) MAR Mem, Read, 0 0 X X X IF2 (00) IF3 (000) Request, Mem MBR 0 0 X X X IF3 (000) IF3 (000) MBR IR 0 X X X IF3 (000) OD (00) 0 X 0 0 X OD (00) LD0 (00) 0 X 0 X OD (00) ST0 (00) 0 X 0 X OD (00) AD0 (0) 0 X X OD (00) BR0 (0) CS 50 - Fall 2005 Lec #4: Control Implementation - 4

8 Moore Machine State Table Reset Wait IR<5> IR<4> AC<5> Current State Next State Register Transfer Ops 0 X X X X LD0 (00) LD (0) IR MAR 0 X X X LD (0) LD (0) MAR Mem, Read, 0 0 X X X LD (0) LD2 (000) Request, Mem MBR 0 X X X X LD2 (000) IF0 (000) MBR AC 0 X X X X ST0 (00) ST (00) IR MAR, AC MBR 0 X X X ST (00) ST (00) MAR Mem, Write, 0 0 X X X ST (00) IF0 (000) Request, MBR Mem 0 X X X X AD0 (0) AD (00) IR MAR 0 X X X AD (00) AD (00) MAR Mem, Read, 0 0 X X X AD (00) AD2 (0) Request, Mem MBR 0 X X X X AD2 (0) IF0 (000) MBR + AC AC 0 X X X 0 BR0 (0) IF0 (000) 0 X X X BR0 (0) BR () 0 X X X X BR () IF0 (000) IR PC CS 50 - Fall 2005 Lec #4: Control Implementation - 5 Moore Machine State Transition Table Observations: Extensive use of Don't Cares Inputs used only in a small number of state e.g., AC<5> examined only in BR0 state IR<5:4> examined only in OD state Some outputs always asserted in a group ROM-based implementations cannot take advantage of don't cares However, ROM-based implementation can skip state assignment step CS 50 - Fall 2005 Lec #4: Control Implementation - 6

9 Moore Machine Implementation Assume PLA implementation style First idea: run ESPRESSO with naive state assignment 2 product terms Compare with 52 product terms in ROM implementation!.i 9.o 4.ilb reset wait ir5 ir4 ac5 q3 q2 q q0.ob p3 p2 p p0.p e CS 50 - Fall 2005 Lec #4: Control Implementation - 7.i 9.o 4.ilb reset wait ir5 ir4 ac5 q3 q2 q q0.ob p3 p2 p p0.p e Moore Machine Implementation NOVA assignment does better NOVA State Assignment SUMMARY onehot_products = 22 best_products = 8 best_size = 44 8 product terms improves on 2! states[0]:if0 Best code: 0000 states[]:if Best code: 0 states[2]:if2 Best code: states[3]:if3 Best code: 0 states[4]:od Best code: 000 states[5]:ld0 Best code: 000 states[6]:ld Best code: 00 states[7]:ld2 Best code: 000 states[8]:st0 Best code: 00 states[9]:st Best code: 00 states[0]:ad0 Best code: 0 states[]:ad Best code: 000 states[2]:ad2 Best code: 00 states[3]:br0 Best code: 00 states[4]:br Best code: 00 states[5]:res Best code: 0 CS 50 - Fall 2005 Lec #4: Control Implementation - 8

10 Synchronous Mealy Machines Standard Mealy Machine has asynchronous outputs Change in response to input changes, independent of clock Revise Mealy Machine design so outputs change only on clock edges One approach: non-overlapping clocks Synchronizer Circuitry at at Inputs Inputs and and Outputs Outputs A D Q A' ƒ D Q ƒ' Output Logic STATE A STATE A STATE A' ƒ D Q Output Logic ƒ D Q ƒ' Output Logic CS 50 - Fall 2005 Lec #4: Control Implementation - 9 Synchronous Mealy Machines Case I: Synchronizers at Inputs and Outputs A A' cycle 0 cycle cycle 2 S0 S A/ƒ ƒ ƒ' S2 A asserted in Cycle 0, ƒ becomes asserted after 2 cycle delay! This is clearly overkill! CS 50 - Fall 2005 Lec #4: Control Implementation - 20

11 Synchronous Mealy Machine Case II: Synchronizers on Inputs cycle 0 cycle cycle 2 S0 A/ƒ S0 A S S A' A'/ƒ ƒ A asserted in Cycle 0, ƒ follows in next cycle Same as using delayed signal (A') in Cycle! CS 50 - Fall 2005 Lec #4: Control Implementation - 2 Synchronous Mealy Machines Case III: Synchronized Outputs cycle 0 cycle cycle 2 A ƒ S0 S A/ƒ ƒ' A asserted during Cycle 0, ƒ' asserted in next cycle Effect of ƒ delayed one cycle CS 50 - Fall 2005 Lec #4: Control Implementation - 22

12 Synchronous Mealy Machines Implications for Processor FSM Already Derived Consider inputs: Reset, Wait, IR<5:4>, AC<5> Latter two already come from registers, and are sync'd to clock Possible to load IR with new instruction in one state & perform multiway branch on opcode in next state Best solution for Reset and Wait: synchronized inputs» Place D flipflops between these external signals and the» control inputs to the processor FSM» Sync'd versions of Reset and Wait delayed by one clock cycle CS 50 - Fall 2005 Lec #4: Control Implementation - 23 Time State Divide and Conquer Overview Classical Approach: Monolithic Implementations Alternative "Divide & Conquer" Approach:» Decompose FSM into several simpler communicating FSMs» Time state FSM (e.g., IFetch, Decode, Execute)» Instruction state FSM (e.g., LD, ST, ADD, BRN)» Condition state FSM (e.g., AC < 0, AC 0) CS 50 - Fall 2005 Lec #4: Control Implementation - 24

13 Time State (Divide & Conquer) Time State FSM Most instructions follow same basic sequence Differ only in detailed execution sequence Time State FSM can be parameterized by opcode and AC states Instruction State: stored in IR<5:4> Condition State: stored in AC<5> =00 =0 IR =0 = LD ST ADD BRN AC < 0 AC<5>=0 AC? 0 T0 T T2 T3 T4 T5 T6 T7 AC<5>= CS 50 - Fall 2005 Lec #4: Control Implementation - 25 BRN AC _ 0/ (LD + ST + ADD) BRN + (ST Wait)/ (LD + ADD) Wait Time State (Divide & Conquer) Generation of Microoperations 0 PC: Reset PC + PC: T0 PC MAR: T0 MAR Memory Address Bus: T2 + T6 (LD + ST + ADD) Memory Data Bus MBR: T2 + T6 (LD + ADD) MBR Memory Data Bus: T6 ST MBR IR: T4 MBR AC: T7 LD AC MBR: T5 ST AC + MBR AC: T7 ADD IR<3:0> MAR: T5 (LD + ST + ADD) IR<3:0> PC: T6 BRN Read/Write: T2 + T6 (LD + ADD) 0 Read/Write: T6 ST Request: T2 + T6 (LD + ST + ADD) CS 50 - Fall 2005 Lec #4: Control Implementation - 26

14 Jump Counter Concept Implement FSM using MSI functionality: counters, mux, decoders Pure jump counter: only one of four possible next states N HOLD CLR CNT LOAD 0 N+ XX Single "Jump State" function of the current state Hybrid jump counter: Multiple "Jump States" function of current state + inputs CS 50 - Fall 2005 Lec #4: Control Implementation - 27 Jump Counters Pure Jump Counter Inputs Count, Load, Clear Logic Clear Load Count CLOCK Jump State Logic Synchronous Counter State Register NOTE: No inputs to jump state logic Logic blocks implemented via discrete logic, PLAs, ROMs CS 50 - Fall 2005 Lec #4: Control Implementation - 28

15 Jump Counters Problem with Pure Jump Counter Difficult to implement multi-way branches OD 4 OD0 Extra States: 5 8 OD BR0 LD0 ST0 AD0 BR0 Logical State Diagram 6 OD2 9 AD0 7 0 LD0 ST0 Pure Jump Counter State Diagram CS 50 - Fall 2005 Lec #4: Control Implementation - 29 Jump Counters Hybrid Jump Counter Inputs Count, Load, Clear Logic Load Count Clear CLOCK Jump State Logic Synchronous Counter State Register Load inputs are function of state and FSM inputs CS 50 - Fall 2005 Lec #4: Control Implementation - 30

16 Jump Counters RES 0 Reset Implementation Example IF0 IF 2 State assignment attempts to take advantage of sequential states IF2 OD 3 4 LD0 5 ST0 8 AD0 0 BR0 3 LD 6 ST 9 AD LD2 7 AD2 2 CS 50 - Fall 2005 Lec #4: Control Implementation - 3 Jump Counters Implementation Example, Continued CNT = (s0 + s5 + s8 + s0) + Wait (s + s3) + Wait (s2 + s6 + s9 + s) CNT = Wait (s + s3) + Wait (s2 + s6 + s9 + s) CLR = Reset + s7 + s2 + s3 + (s9 Wait) CLR = Reset s7 s2 s3 (s9 + Wait) LD = s4 Contents of Jump State ROM Address Contents (Symbolic State) 00 (LD0) 000 (ST0) 00 (AD0) 0 (BR0) CS 50 - Fall 2005 Lec #4: Control Implementation - 32

17 Jump Counters /S9 Wait Implementation Example, continued Wait /S /S9 /S6 /S3 /S2 /S OR IR5 IR4 /Reset /S7 /S2 /S3 Cnt PAL Wait S S9 S6 HOLD S3 S2 S Jump State IR<5> IR<4> AND Implement CLR CNT /S P 0 T 2 6 D 5 C Wait B A LOAD CLR Implement CNT using active lo PAL 63 5 RCO QD QC 2 QB 3 QA 4 /Reset /Wait 9 8 CS 50 - Fall 2005 Lec #4: Control Implementation - 33 G2 G 20 D 2 C 22 B 23 A NOTE: Active lo outputs from decoder /S5 /S4 /S3 /S2 /S /S0 /S9 /S8 /S7 /S6 /S5 /S4 /S3 /S2 /S /S0 Jump Counter CLR, CNT, LD implemented via Mux Logic CLR = CLRm + Reset CLR = CLRm + Reset 0 0 /CLRm /Reset Reset Wait /CLR Jump State IR5 IR<5> IR4 IR<4> /Reset /Wait CNT /LD /CLR P T D C B A LOAD CLR 63 RCO QD QC QB QA G2 G D C B A \S3 \S2 \S \S0 \S9 \S8 \S7 \S6 \S5 \S4 \S3 \S2 \S \S0 Active Lo outputs: hi input inverted at the output Note that CNT is active hi on counter so invert MUX inputs! S3 S2 S S0 G E5 50 E4 + E3 + E2 E E0 E9 E8 E7 E6 E5 E4 E3 Wait E2 /Wait E E0 S3 S2 S S0 G G E5 50 E5 50 E4 E4 E3 E3 E2 E2 E E E0 E0 /Wait E9 E9 EOUT 0 E8 E8 EOUT CNT /CLRm EOUT E7 E6 E5 E4 E3 E2 E E0 + S3 S2 S S0 E7 E6 E5 E4 E3 E2 E E0 /LD CS 50 - Fall 2005 Lec #4: Control Implementation - 34

18 Jump Counters Microoperation implementation 0 PC = Reset PC + PC = S0 PC MAR = S0 MAR Memory Address Bus = Wait (S + S2 + S5 + S6 + S8 + S9 + S + S2) Memory Data Bus MBR = Wait (S2 + S6 + S) MBR Memory Data Bus = Wait (S8 + S9) MBR IR = Wait S3 MBR AC = Wait S7 AC MBR = IR5 IR4 S4 AC + MBR AC = Wait S2 IR<3:0> MAR = (IR5 IR4 + IR5 IR4 + IR5 IR4) S4 IR<3:0> PC = AC5 S3 Read/Write = Wait (S + S2 + S5 + S6 + S + S2) 0 Read/Write = Wait (S8 + S9) Request = Wait (S + S2 + S5 + S6 + S8 + S9 + S + S2) Jump Counters: CNT, CLR, LD function of current state + Wait Why not store these as outputs of the Jump State ROM? Make Wait and Current State part of ROM address 32 x as many words, 7 bits wide CS 50 - Fall 2005 Lec #4: Control Implementation - 35 Controller Implementation Summary (Part I!) Control Unit Organization Register transfer operation Classical Moore and Mealy machines Time State Approach Jump Counter Next Time:» Branch Sequencers» Horizontal and Vertical Microprogramming CS 50 - Fall 2005 Lec #4: Control Implementation - 36