SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology

Transcription

1 SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology Clément Champeix (1)(2), Nicolas Borrel (1)(3), Jean-Max Dutertre (2), Bruno Robisson (4), Mathieu Lisart (1) and Alexandre Sarafianos (1) (1) STMicroelectronics Secure Microcontrollers Division (SMD), Rousset France (2) École Nationale Supérieure des Mines de Saint-Etienne Laboratoire Secure Architectures and Systems (LSAS) Centre de Microélectronique de Provence, Gardanne, France (3) Aix Marseille Université CNRS, Université de Toulon, IM2NP UMR 7334, 13397, Marseille, France (4) CEA Cadarache 13108, Saint-Paul-lez-Durance, France 28 th IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium University of Massachusetts Amherst Tuesday October 13, 2015

2 2 Introduction and state of the art

3 Introduction Laser fault injection may be used to alter the behavior of an integrated circuit (IC) e.g. retrieve/modify secret data in integrated circuit 3 Laser fault injection Secret code 4206

4 Introduction Laser fault injection may be used to alter the behavior of an integrated circuit (IC) e.g. retrieve/modify secret data in integrated circuit 3 Laser fault injection Secret code 4206 Sensors are used to catch and flag when a perturbation is induced

5 Introduction Laser fault injection may be used to alter the behavior of an integrated circuit (IC) e.g. retrieve/modify secret data in integrated circuit 3 Laser fault injection Secret code 4206 Sensors are used to catch and flag when a perturbation is induced Logical gates designs may be robust to laser injection

6 Introduction Laser fault injection may be used to alter the behavior of an integrated circuit (IC) e.g. retrieve/modify secret data in integrated circuit 3 Laser fault injection Secret code 4206 Sensors are used to catch and flag when a perturbation is induced Logical gates designs may be robust to laser injection Models make it possible to simulate the response of ICs to laser pulses

7 Introduction Laser fault injection may be used to alter the behavior of an integrated circuit (IC) e.g. retrieve/modify secret data in integrated circuit 3 Laser fault injection Secret code 4206 Sensors are used to catch and flag when a perturbation is induced Logical gates designs may be robust to laser injection Models make it possible to simulate the response of ICs to laser pulses This presentation reports the experimental analyze of a D Flip-Flop cell, designed in CMOS 40 nm, under Photoelectric Laser Stimulation (PLS) and the upgrade of electrical laser models

8 NMOS OFF PMOS ON Introduction DUT Experiments Modeling Conclusion Single-Events Effects (SEE) 4 Example: Laser effect on a CMOS inverter with its input at low level Sensitive junction is the Drain of NMOS which is in OFF state IN 0 1 OUT Sensitive junction

9 NMOS OFF PMOS ON Introduction DUT Experiments Modeling Conclusion Single-Events Effects (SEE) 4 Example: Laser effect on a CMOS inverter with its input at low level Sensitive junction is the Drain of NMOS which is in OFF state Photocurrent flows through the Psubstrate IN 0 1 OUT

10 NMOS OFF PMOS ON Introduction DUT Experiments Modeling Conclusion Single-Events Effects (SEE) 4 Example: Laser effect on a CMOS inverter with its input at low level Sensitive junction is the Drain of NMOS which is in OFF state Photocurrent flows through the Psubstrate State of the output from 1 to 0 IN OUT

11 NMOS OFF PMOS ON Introduction DUT Experiments Modeling Conclusion Single-Events Effects (SEE) 4 Example: Laser effect on a CMOS inverter with its input at low level Sensitive junction is the Drain of NMOS which is in OFF state Photocurrent flows through the Psubstrate State of the output from 1 to 0 IN 0 IN OUT OFF NMOS OUT 1 0 PMOS ON P+ N+ N+ P+ P+ N+ Nwell Laser Psubtrate

12 Example: Laser effect on a Latch Single-Events Effects (SEE) 5 Single-Events Upset (SEU) for Bit Set and Bit Reset

13 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set (a) Bit Set

14 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set (a) Bit Set

15 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set State of the output from 0 to (a) Bit Set CLK LASER TRIG OUT Acquisition

16 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set State of the output from 0 to (a) Bit Set CLK LASER TRIG OUT Acquisition

17 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set State of the output from 0 to 1 Bit Reset (a) Bit Set (b) Bit Reset CLK LASER TRIG OUT Acquisition

18 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set State of the output from 0 to 1 Bit Reset (a) Bit Set (b) Bit Reset CLK LASER TRIG OUT Acquisition

19 Example: Laser effect on a Latch Single-Events Effects (SEE) Single-Events Upset (SEU) for Bit Set and Bit Reset 5 Bit Set State of the output from 0 to 1 Bit Reset State of the output from 1 to (a) Bit Set (b) Bit Reset CLK CLK LASER TRIG LASER TRIG OUT OUT Acquisition Acquisition

20 Latch sensitivity 6 Schematic of a latch cell laser sensitivity area with input at 0 and 1

21 NMOS ON NMOS OFF PMOS OFF PMOS ON Introduction DUT Experiments Modeling Conclusion Latch sensitivity 6 Schematic of a latch cell laser sensitivity area with input at 0 and 1 The purple arrows give the photocurrent directions and its strength (a) Input at 0 IN MP4 0 1 OUT MN4 MP5 MN5 Bit reset High laser sensitivity Bit set Low laser sensitivity

22 NMOS ON NMOS OFF NMOS OFF PMOS OFF PMOS ON NMOS ON PMOS ON PMOS OFF Introduction DUT Experiments Modeling Conclusion Latch sensitivity 6 Schematic of a latch cell laser sensitivity area with input at 0 and 1 The purple arrows give the photocurrent directions and its strength (a) Input at 0 (b) Input at 1 IN MP4 0 1 OUT IN MP4 1 0 OUT MN4 MN4 MP5 MP5 MN5 MN5 Bit reset High laser sensitivity Bit set Low laser sensitivity

23 D Flip Flop description 7 A D Flip-Flop is a memorizing cell Store information and many other uses More than a thousand in an integrated circuit It becomes mandatory to thwart laser attacks (weakness point) Data Clock D CLK Q Output

24 D Flip Flop description 7 A D Flip-Flop is a memorizing cell Store information and many other uses More than a thousand in an integrated circuit It becomes mandatory to thwart laser attacks (weakness point) Data Clock D CLK Q Output D Q CLK/CLK Master CLK/CLK Slave

25 D Flip Flop description 7 A D Flip-Flop is a memorizing cell Store information and many other uses More than a thousand in an integrated circuit It becomes mandatory to thwart laser attacks (weakness point) Data Clock D CLK Q Output D Q CLK/CLK Master CLK/CLK Slave D Flip-Flop functioning Change state at rising edge Memorize during non rising

26 4 steps to impact master or slave latch D Flip Flop evaluations 8

27 4 steps to impact master or slave latch CLK = 1 D Flip Flop evaluations Master Slave (a) CLK= 1 CLK Data inside Master LASER TRIG OUT Acquisition (b) CLK= 1

28 4 steps to impact master or slave latch CLK = 1 CLK = 0 D Flip Flop evaluations Master Slave Master Slave (a) CLK= 1 (c) CLK= 0 Data inside Slave CLK Data inside Master CLK Data inside Master LASER TRIG LASER TRIG OUT OUT Acquisition (b) CLK= 1 (d) CLK= 0 Acquisition

29 4 steps to impact master or slave latch CLK = 1 CLK = 0 D Flip Flop evaluations Master Slave Master Slave (a) CLK= 1 (c) CLK= 0 Data inside Slave CLK Data inside Master CLK Data inside Master LASER TRIG LASER TRIG OUT OUT Acquisition (b) CLK= 1 (d) CLK= 0 Acquisition 4 steps

30 9 Device Under Test (DUT)

31 Theoretical hypothesis Sensitive areas on schematic D Flip-Flop schematic 40 nm CMOS technology 10

32 Introduction DUT Experiments Modeling Conclusion Theoretical hypothesis Sensitive areas on schematic D Flip-Flop schematic 40 nm CMOS technology 10 Master Slave IN MP1 CLKD MP4 CLKN MP8 IN MP2 MP6 L1_I L1_O L2_I L2_O MN1 CLKN MN2 MN6 MN3 MN7 MN4 MN8 CLKD CLKD CLKN MP3 MP5 MP7 MP9 net01 net02 MP10 MN10 OUT CLK MP11 CLKN MN11 MP12 CLKD MN12 MN5 CLK= 1 MN9 CLK= 0 Sensitive areas for Bit Reset Sensitive areas for Bit Set

33 Theoretical hypothesis Sensitive areas on corresponding layout D Flip-Flop layout 40 nm CMOS technology 11

34 2 µm Introduction DUT Experiments Modeling Conclusion D Flip-Flop layout 40 nm CMOS technology Theoretical hypothesis Sensitive areas on corresponding layout 4 µm MP1 MP2 MP3 MP5 MP4 MP7 MP6 MP8 MP9 MP10 MP12 MP11 11 Master Slave MN1 MN2 MN3 MN5 MN4 MN6 MN7 MN8 MN9 MN10 MN12 MN11 Sensitive areas for Bit Reset Sensitive areas for Bit Set

35 12 Experiments

36 Experiments settings 13 Experimental set up Wavelength: 1030 nm (near Infra Red) Spot size: ~ 1 µm (100X lens) Laser through silicon substrate backside Laser power: 0.7 nj Laser pulse duration: 30 ps Cartography step: 0.2 µm

37 Experimental results Experiments results nm CMOS technology

38 Experimental results Experiments results nm CMOS technology Master Slave Missing fault area Bit Reset Bit Set

39 2 µm Introduction DUT Experiments Modeling Conclusion Experimental results Experiments results 14 Basically fit with theoretical hypothesis One missing fault area because of the capacitor and resistivity of the net 40 nm CMOS technology 4 µm MP1 MP2 MP3 MP5 MP4 MP6 MP7 MP9 MP8 MP10 MP12 MP11 Master Slave Master Slave MN1 MN2 MN3 MN4 MN5 MN6 MN7 MN8 MN12 MN9 MN10 MN11 Bit Reset Bit Set Missing fault area Sensitive areas for Bit Reset Sensitive areas for Bit Set (a) Theoretical hypothesis (b) Experimental

40 Introduction DUT Experiments Modeling Conclusion D Flip-Flop schematic 40 nm CMOS technology 15 IN CLK MP1 CLKD MP4 CLKN MP8 IN MP2 MP6 L1_I L1_O L2_I L2_O MN2 MN1 CLKN MP3 MP11 MP12 CLKN CLKD MN3 CLKD net01 MN4 MP5 MN5 MN6 CLKD MN7 MN8 CLKN MP7 MP9 net02 Missing fault area MN9 MP10 MN10 OUT MN11 MN12 Sensitive areas for Bit Reset Sensitive areas for Bit Set

41 Introduction DUT Experiments Modeling Conclusion IN CLK MN4 MP5 MN5 D Flip-Flop schematic MP1 CLKD MP4 CLKN MP8 IN MP2 MP6 L1_I L1_O L2_I L2_O MN1 MN2 MP11 CLKN CLKN MP3 MP12 CLKD MN3 CLKD net01 MP6 MN6 MN6 CLKD MP7 MN7 CLKN net02 MN8 Missing fault area 40 nm CMOS technology MP9 MN9 MP10 MN10 OUT MP10 MN10 15 MN11 MN12 Sensitive areas for Bit Reset Sensitive areas for Bit Set

42 Introduction DUT Experiments Modeling Conclusion IN CLK MN4 MP5 MN5 D Flip-Flop schematic MP1 CLKD MP4 CLKN MP8 IN MP2 MP6 L1_I L1_O L2_I L2_O MN1 MN2 MP11 CLKN CLKN MP3 MP12 CLKD MN3 CLKD net01 MP6 MN6 MN6 CLKD MP7 MN7 CLKN net02 MN8 Missing fault area 40 nm CMOS technology MP9 MN9 MP10 MN10 OUT MP10 MN10 15 MN11 MN12 Sensitive areas for Bit Reset Sensitive areas for Bit Set MN10 and MP10 > MN6 and MP6 L2_O cap/res > L1_O cap/res

43 16 Modeling

44 Photocurrent (%) Introduction DUT Experiments Modeling Conclusion Modeling settings 17 Electrical modeling (Photoelectrical laser stimulation model) Coefficient adjustment for picosecond laser pulse duration Iph source Laser_trigger Subckt_Iph V n Iph = f(v) Power 1 Power 2 Power 3 Power p Time (ns) I ph 1 γ (av b)α gauss Pulse width W coef I ph_z References: Equations model and applications courtesy Alexandre Sarafianos s publications

45 Photocurrent (%) Introduction DUT Experiments Modeling Conclusion Modeling settings 17 Electrical modeling (Photoelectrical laser stimulation model) Coefficient adjustment for picosecond laser pulse duration V is the reverse-biased voltage Laser_trigger Subckt_Iph V n p Iph = f(v) Iph source Power 1 Power 2 Power 3 Power Time (ns) a and b depend on laser power γ is an amplification attenuation coefficient α gauss is the sum of two gaussian functions (spatial dependency) Pulse width considers laser power duration I ph 1 γ (av b)α gauss Pulse width W coef I ph_z W coef is an exponential function for the wafer thickness I ph_z is a curve function considering the focus effect of laser lens References: Equations model and applications courtesy Alexandre Sarafianos s publications

46 Modeling results Modeling results nm CMOS technology

47 Modeling results Modeling results nm CMOS technology Master Slave Bit Reset Bit Set No post layout simulation Photoelectrical only

48 2 µm Introduction DUT Experiments Modeling Conclusion Modeling results Basically fit with theoretical hypothesis and experimental 4 µm MP1 MP2 MP3 MP5 MP4 MP7 MP6 MP8 MP9 MP10 MP12 MP11 Modeling results nm CMOS technology Master Slave Master Slave MN1 MN3 MN4 MN7 MN8 MN12 MN2 MN5 MN6 MN9 MN10 MN11 Sensitive areas for Bit Reset Sensitive areas for Bit Set (a) Theoretical hypothesis Bit Reset Bit Set (b) Experimental Missing fault area Master Slave Bit Reset Bit Set No post layout simulation Photoelectrical only (c) Modeling

49 19 Conclusion and perspectives

50 Conclusion and perspectives 20 Conclusion Analysis of laser fault injection of a CMOS 40nm D Flip-Flop cell and the upgrading of photoelectrical laser stimulation models

51 Conclusion and perspectives 20 Conclusion Analysis of laser fault injection of a CMOS 40nm D Flip-Flop cell and the upgrading of photoelectrical laser stimulation models Good correlation between photoelectrical hypothesis, experiments and models

52 Conclusion and perspectives 20 Conclusion Analysis of laser fault injection of a CMOS 40nm D Flip-Flop cell and the upgrading of photoelectrical laser stimulation models Good correlation between photoelectrical hypothesis, experiments and models Perspectives and future works The models will be enhance to take account capacitors and resistivity of the nets

53 Conclusion and perspectives 20 Conclusion Analysis of laser fault injection of a CMOS 40nm D Flip-Flop cell and the upgrading of photoelectrical laser stimulation models Good correlation between photoelectrical hypothesis, experiments and models Perspectives and future works The models will be enhance to take account capacitors and resistivity of the nets Flip-flops will be designed and tested to validate the model and develop robust cells to laser fault injection

54 Conclusion and perspectives 20 Conclusion Analysis of laser fault injection of a CMOS 40nm D Flip-Flop cell and the upgrading of photoelectrical laser stimulation models Good correlation between photoelectrical hypothesis, experiments and models Perspectives and future works The models will be enhance to take account capacitors and resistivity of the nets Flip-flops will be designed and tested to validate the model and develop robust cells to laser fault injection This first step model presented could be an interesting tool for designers who want to build robust gates or test the robustness of our designs

55 21 Thank you for your attention 28th IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium University of Massachusetts Amherst Tuesday October 13, 2015