Chapter # 5: Arithmetic Circuits

Transcription

1 Chapter # 5: rithmetic Circuits Contemporary Logic Design 5- Number ystems Representation of Negative Numbers Representation of positive numbers same in most systems Major differences are in how negative numbers are represented Three major schemes: sign and magnitude ones complement twos complement ssumptions: we'll assume a bit machine word 6 different values can be represented roughly half are positive, half are negative 5-2

2 Number ystems ign and Magnitude Representation = + = - - High order bit is sign: = positive (or zero), = negative Three low order bits is the magnitude: () thru 7 () n- Number range for n bits = +/-2 - Representations for 5-3 Number ystems ign and Magnitude Cumbersome addition/subtraction Must compare magnitudes to determine sign of result Ones Complement N is positive number, then N is its negative 's complement n N = (2 - ) - N Example: 's complement of 7 2 = - = -7 = hortcut method: = -7 in 's comp. simply compute bit wise complement -> 5-

3 Number ystems Ones Complement = + = - - ubtraction implemented by addition & 's complement till two representations of! This causes some problems ome complexities in addition 5-5 Number Representations Twos Complement like 's comp except shifted one position clockwise = + = - - Only one representation for One more negative number than positive number 5-6

4 Number ystems Twos Complement Numbers n N* = 2 - N Example: Twos complement of 7 2 = sub 7 = = repr. of -7 Example: Twos complement of -7 2 = sub -7 = = repr. of 7 hortcut method: Twos complement = bitwise complement + -> + -> (representation of -7) -> + -> (representation of 7) 5-7 Number Representations ddition and ubtraction of Numbers ign and Magnitude result sign bit is the same as the operands' sign (-3) -7 when signs differ, operation is subtract, sign of result depends on sign of number with the larger magnitude

5 Number ystems ddition and ubtraction of Numbers Ones Complement Calculations (-3) 7-7 End around carry End around carry 5-9 Number ystems ddition and ubtraction of inary Numbers Twos Complement Calculations (-3) 7-7 If carry-in to sign = carry-out then ignore carry if carry-in differs from carry-out then overflow impler addition scheme makes twos complement the most common choice for integer number systems within digital systems 5-

6 Number ystems Overflow Conditions Overflow Overflow No overflow No overflow Overflow when carry in to sign does not equal carry out 5- Half dder With twos complement numbers, addition is sufficient i i um Carry i i i i um = i i + i i = i + i Carry = i i i um i Half-adder chematic Carry 5-2

7 Full dder Cascaded Multi-bit dder C3 2 C2 C - usually interested in adding more than two bits - this motivates the need for the full adder 5-3 Full dder CI CI CI = CI xor xor = CI + CI + = CI ( + ) + 5-

8 Networks for inary ddition Full dder/half dder tandard pproach: 6 Gates CI CI lternative Implementation: 5 Gates Half dder + Half dder + + CI CI ( + ) CI + + CI ( xor ) = + CI + CI 5-5 dder/ubtractor el el el el + CI + CI + CI + CI dd/ubtract 3 2 Overflow - = + (-) =

9 Carry Lookahead Circuits Critical delay: the propagation of carry from low to high order stages late two gate delays to compute C stage C C C final sum and carry 5-7 Carry Lookahead Circuits Critical delay: the propagation of carry from low to high order stages, C Valid, C2 Valid 2, C3 Valid 3, C Valid + worst case addition T T2 T T6 T8 T: Inputs to the adder are valid T2: tage carry out (C) T: tage carry out (C2) T6: tage 2 carry out (C3) - 2 delays to compute sum - but last carry not ready until 6 delays later T8: tage 3 carry out (C) 5-8

10 Carry Lookahead Logic Carry Generate Gi = i i must generate carry when = = Carry Propagate Pi = i xor i carry in will equal carry out here um and Carry can be reexpressed in terms of generate/propagate: i = i xor i xor Ci = Pi xor Ci Ci+ = i i + i Ci + i Ci = i i + Ci (i + i) = i i + Ci (i xor i) = Gi + Ci Pi 5-9 Reexpress the carry logic as follows: C = G + P C C2 = G + P C = G + P G + P P C C3 = G2 + P2 C2 = G2 + P2 G + P2 P G + P2 P P C C = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G + P3 P2 P G + P3 P2 P P C Each of the carry equations can be implemented in a two-level logic network Variables are the adder inputs and carry in to stage! 5-2

11 Carry Lookahead Logic G i = i i Pi = i xor i C = G + P C = C 2 = G + P C = + ( xor ) C 3 = G 2 + P 2 C 2 = ( 2 xor 2 )( + ( xor ) ) C = G 3 + P 3 C 3 = ( 3 xor 3)( ( 2 xor 2)( + ( xor ) )) 5-2 Carry Lookahead Implementation i i Ci gate delay 2 gate delays dder with Propagate and Generate Outputs gate delay Increasingly complex logic C P G C P P G P G C C2 C P P P2 G P P2 G P2 G2 C3 C P P P2 P3 G P P2 P3 G P2 P3 G2 P3 C G3 5-22

12 Cascaded Carry Lookahead C Carry lookahead logic generates individual @ sums computed much faster C 2 2 C Cascaded Carry Lookahead C [5-2] [5-2] C [-8] [-8] 6 -bit dder 2 -bit dder P G @3 C 8 [7-] [7-] C [3-] [3-] -bit dder -bit dder P G C C P 3 G 3 C 3 P 2 G 2 C 2 P G C P G Lookahead Carry Unit C P 3- G @5 bit adders with internal carry lookahead second level carry lookahead unit, extends lookahead to 6 bits 5-2

13 Carry elect dder Redundant hardware to make carry calculation go faster C 8 -it dder [7:] dder Low C C 8 -it dder [7:] dder High 2: Mux C -it dder [3:] C C compute the high order sums in parallel one addition assumes carry in = the other assumes carry in = 5-25 rithmetic Logic Unit Design M =, Logical itwise Operations Function Fi = i Fi = not i Fi = i xor i Fi = i xnor i Comment Input i transferred to output Complement of i transferred to output Compute XOR of i, i Compute XNOR of i, i M =, C =, rithmetic Operations F = F = not F = plus F = (not ) plus M =, C =, rithmetic Operations Input passed to output Complement of passed to output um of and um of and complement of F = plus F = (not ) plus F = plus plus F = (not ) plus plus Increment Twos complement of Increment sum of and minus Logical and rithmetic Operations Not all operations appear useful, but "fall out" of internal logic 5-26

14 rithmetic Logic Unit Design ample LU Clever Multi-level Logic Implementation i X i M 2 Ci = blocks i Happens when operations involve i only ame is true for Ci when M = ddition happens when M = X2 3 O X3 Ci+ Fi 8 Gates (but 3 are XOR) i, Ci to Xor gates X2, X3 =, X passes =, X passes rithmetic Mode: Or gate inputs are i Ci and i (i xor Ci) Logic Mode: Cascaded XORs form output from i and i TTL LU 3 election M = M =, rithmetic Functions 2 Logic Function Cn = F = not F = nand F = (not ) + F = F = nor F = not F = xnor F = + not F = (not ) F = xor F = F = + F = F = (not ) F = F = F = minus F = minus F = (not ) minus F = minus F = plus ( + not ) F = plus ( + not ) F = minus minus F = + not F = plus ( + ) F = plus F = (not ) plus ( + ) F = ( + ) F = F = plus F= (not ) plus F = Cn = F = F = F = (not ) F = zero F = plus ( + not ) plus F = plus ( + not ) plus F = ( + not ) plus F = minus F = ( + not ) plus F = plus ( + ) plus F = (not ) plus ( + ) plus F = ( + ) plus F = plus plus F = plus plus F = (not ) plus plus F = plus 5-28

15 78 TTL LU Note that the sense of the carry in and out are OPPOITE from the input bits Cn 8 M 8 F3 F2 F F = Cn+ 6 G 7 P P3 P2 P P G3 G2 G G 3 Cn P G Cn+z Cn+y Cn+x Fortunately, carry lookahead generator maintains the correct sense of the signals 5-29 CD ddition 5 = 3 = = 8 5 = 8 = = 3! Problem when digit sum exceeds 9 olution: add 6 () if sum exceeds 9! 5 = 8 = 6 = = 3 in CD 9 = 7 = = 6 in binary 6 = = 6 in CD 5-3

16 CD ddition F CI F CI F CI F CI Cin XX 2 XX F CI F CI Cout 3 2 dd to sum whenever it exceeds (XX or XX) 5-3 Combinational Multiplier asic Concept multiplicand multiplier * (3) () Partial products (3) product of 2 -bit numbers is an 8-bit number 5-32

17 Partial Product ccumulation Partial Product ccumulation F H H H F F F F F F H F Note use of parallel carry-outs to form higher order sums 2 dders, if full adders, this is 6 gates each = 72 gates 6 gates form the partial products total = 88 gates! 5-3

18 Case tudy: 8 x 8 Multiplier TTL Multipliers G G Y Y Y Y G Y Y Y Y G Y 6 Y Y 2 Y Y 7 Y 5 Y 3 Y Two chip implementation of x multipler 5-35