# An Efficient RNS to Binary Converter Using the Moduli Set {2n + 1, 2n, 2n 1}

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2 components. The critical path analysis, which takes into consideration hardware implementation details, indicates that the proposed converter outperforms other state of the art converters in terms of speed at the expense of same or lower area. The rest of the article is organised as follows: Section II presents the necessary background. In Section III we describe the proposed algorithm. Section IV presents the hardware realization of the proposed algorithm and a comparison with the state of the art, while the paper is concluded in Section V. II. BACKGROUND RNS is defined in terms of a set of relatively prime moduli set {m i } i1,n such that gcd(m i, m j ) 1 for i j, where gcd means the greatest common divisor of m i and m j, while n i1 m i, is the dynamic range. The residues of a decimal number can be obtained as x i mi thus can be represented in RNS as (x 1, x,..., x n ), 0 x i < m i. This representation is unique for any integer [0, 1]. We note here that in this paper we use mi to denote the mod m i operation and the operator Θ to represent the operation of addition, subtraction, or multiplication. Given any two integer numbers K and L RNS represented by K (k 1, k, k 3,..., k n ) and L (l 1, l, l 3,..., l n ), respectively, W KΘL, can be calculated as W (w 1, w, w 3,..., w n ), where w i k i Θl i mi, for i 1, n. This means that the complexity of the calculation of the Θ operation is determined by the number of bits required to represent the residues and not by the one required to represent the input operands. This creates the premises for high speed arithmetic and for example it has been proved that RNS based addition can be performed in O(log(log(n))) delay for unrestricted moduli and in O(log(n)) for n and n 1 moduli [4]. For a moduli set {m i } i1,n with the dynamic range n i1 m i, the residue number (x 1, x,,..., x n ) can be converted into the decimal number, according to the Chinese Reminder Theorem, as follows [8]: n 1 mi i i x i, (1) i1 where n i1 m i, i m i, and i 1 is the multiplicative inverse of i with respect to m i. This general scheme can be actually simplified when certain moduli sets of interests like {n + 1, n, n 1} are utilized. For this moduli set the following relations have been derived for (x 1 + ) even and odd, respectively, in [7]: m m 3 + m m 3 x 1 m 1 m 3 x + m 1m () x 1 m 1 m 3 x + m 1m (3) For the same moduli set, the following relation, which uses smaller multipliers when compared to Equations () and (3) have been presented in [1]: (x1 ) + z 0 n x + m (x1 x + ) + z 0 n + n, (4) m 1 m 3 where z 0 is the OR over the least significant bits of x 1 and. In the following section we assume the same moduli sets {n + 1, n, n 1} and we introduce an RNS to decimal converter based on Equation (1) by eliminating the computation of the required multiplicative inverses. By doing that we obtain exactly the same relations as Equations () and (3). Further we simplify these expressions such that we obtain relations that use smaller multipliers and require lesser number of arithmetic operations when compared to Equation (4). III. PROPOSED ALGORITH Given the RNS number (x 1, x, ) with respect to the moduli set {m 1, m, m 3 } in the form {n + 1, n, n 1}, the proposed algorithm computes the decimal equivalent of this RNS number based on a further simplification of the well-known traditional CRT. First, we demonstrate that the computation of the multiplicative inverses can be eliminated for this moduli set. We further simplify the resulting CRT to get a low complexity implementation that does not require explicit use of modulo operation in the final stage of the computation. Theorem 1: Given the moduli set {n+1, n, n 1} with m 1 n + 1, m n, m 3 n 1 the following hold true: (m 1 m ) 1 m3 n, (5) (m m 3 ) 1 m1 n + 1, (6) (m 1 m 3 ) 1 m n 1. (7) Proof: If it can be demonstrated that n (m 1 m ) m3 1, then n is the multiplicative inverse of (m 1 m ) with respect to m 3. n (m 1 m ) m3 is given by: (n + 1)(n)(n) n 1 (4n + n)n n 1 4n 3 n 1 + n n 1 n n 1 1, thus Equation (5) holds true. In the same way if (n + 1) (m m 3 ) m1 1, then n+1 is the multiplicative inverse of (m m 3 ) with respect

3 to m 1. (n+1) (m m 3 ) m1 is given by: n(n 1)(n+ 1) n+1 n (n+1) n n+1 n (n+1) n+1 + n n+1 n n+1 1, thus Equation( 6) holds true. Again, if (n 1) (m 1 m 3 ) m 1, then n 1 is the multiplicative inverse of (m 1 m 3 ) with respect to m. (n 1) (m 1 m 3 ) m is given by: (n+1)(n 1)(n 1) n 8n 3 4n n+1 n n(4n n 1) n + 1 n n n 1, thus Equation (7) holds true. The following theorem introduces a simplified way to compute the decimal equivalent of the RNS number (x 1, x, ) with respect to the moduli set {m 1, m, m 3 } in the form {n + 1, n, n 1} by simplifying Equation (1) for the specific case n 3. Theorem : The decimal equivalent of the RNS number (x 1, x, ) with respect to the moduli set {m 1, m, m 3 } in the form {n + 1, n, n 1} is computed for (x 1 + ) even and odd, respectively, as follows: m m 3 + m m 3 x 1 m 1 m 3 x + m 1m (8) x 1 m 1 m 3 x + m 1m (9) Proof: Equation (1) for n 3 is given by: 3 1 mi i i x i. (10) i1 By substituting the multiplicative inverse values in Theorem 1 into Equation (10) we obtain the following: (m m 3 )( m + 1)x 1 + (m 1 m 3 )(m 3 )x +(m 1 m )( m ) (m m 3 )( m )x 1 + (m 1 m 3 )(m 1)x +(m 1 m )( m ) ( )x 1 + ( m m 3 )x 1 m 1 m 3 x +( ) + ( m 1m ) (x 1 + ) + (m m 3 )x 1 m 1 m 3 x + (m 1m ) (11) From Equation (11), the following cases may be considered: If (x 1 + ) is even then (x 1 + ) 0. If (x 1 + ) is odd then (x 1 + ). Given that Equation (11) can be re-written for the first and the second case, respectively, as: m m 3 + m m 3 x 1 m 1 m 3 x + m 1m (1) x 1 m 1 m 3 x + m 1m (13) Equations (8), (9), and (11), are exactly the same as to ones derived based on a weighting function in [7] and [5]. Thus the hardware realization based on these equations is the same as the one presented in [7], [5] and [1]. We propose to further simplify (8) and (9) using the following theorem: Theorem 3: Given the RNS number (x 1, x, ) with respect to the moduli set {m 1, m, m 3 } in the form {n + 1, n, n 1}, the decimal equivalent of this RNS number is computed for (x 1 + ) even and odd, respectively, as follows: m m x 1 + m 1 (x 1 + ) m 3 x (14) m m 3 m x 1 +m 1 m m 3 + m (x 1 + ) m 3 x (15) m m 3 Proof: To prove this theorem we use the following lemma presented in [11]: am 1 m1m m 1 a m (16) From Equation (8), we have m m 3 x 1 m 1 m 3 x + m 1m m1 m m 3 m (m 1 )x 1 m 1 m 3 x + m 1m m1 m m 3 x 1 + m 1 m (x 1 + ) m 1 x 1 m 1 m 3 x (17) m1 m m 3 Applying Equation (16) we obtain x 1 + m 1 m (x 1 + ) x 1 m 3 x m m 3, (18) which can be further simplified as: m x 1 + m 1 m (x 1 + ) m 3 x m m 3 (19) thus Equation (14) holds true.

4 From Equation (9), we have m 1 m m 3 + m m 3 x 1 m 1 m 3 x + m 1m m1 m m 3 m 1 m m 3 + m (m 1 )x 1 m 1 m 3 x + m 1m m1 m m 3 x 1 + m 1 m m 3 + m 1m (x 1 + ) m 1 x 1 m 1 m 3 x m1 m m 3 (0) Applying Equation (16) we obtain x 1 +m 1 m m 3 which can be further simplified as + m (x 1 + ) x 1 m 3 x (1), mm 3 m m 3 m x 1 + m 1 + m (x 1 + ) m 3 x () mm 3 thus Equation (15) holds also true. IV. PERFORANCE EVALUATION The converter described in this paper is processing numbers with smaller magnitude than the one proposed in [7]. This can be easily deduced based on the fact that Equations (14) and (15) use modulo m m 3 instead of modulo m 1 m m 3 as required by Equations () and (3). The same holds true also when we compare our proposal with the one in [1] due to the fact that for the considered moduli set the modulo (m m 3 ) in Equations (14) and (15) is always smaller than the modulo (m 1 m 3 ) in Equation (4). ore precisely the modulo used in [1] is with n 1 larger than the one we utilize. Consequently, the numbers involved in Equations (14) and (15) are smaller than those in Equation (4). This results in a reduced complexity and delay of the associated hardware as the smaller the magnitude of the processed operands the less complex are the required functional units that support the calculations. The number of arithmetic operations required for our proposal - Equations (14) and (15) - and for the one in [1] - Equation (4) - are summarized in Table I. As one can observe in the Table our proposal requires less additions but more multiplications. This information however is not sufficient to make a comparison as the Operations [1] Proposed Algorithm Additions 7 3/4 ultiplications 4 Reduced m 1 m 3 m m 3 Table I PERFORANCE COPARISON delay and area of the involved adders and multipliers depend on operand magnitudes and on implementation specific details. Thus a deeper analysis of the required hardware has to be done in order to get a more realistic picture. The hardware required for our proposal is depicted in Figure 1 and the one for the converter in [1] in Figure. Before we further analyze the two schemes we first prove that modulo (m m 3 ) operations in Equations (14) and (15) do not need to be explicitly implemented and this operation can be done by adder AB in Figure 1 with at most one corrective addition/subraction. For that we analyze all the possible cases as follows: 1) (x 1 + ) 0 and x n 1. This results in the most negative value one may get. In this case Equation (14) reduces to m 3 x m m 3. To perform the modulo (m m 3 ) operation we need to do corrective additions. Given that m m 3 + ( m 3 x ) (n)(n 1) ((n 1)(n 1)) 4n n 4n + 4n 1 n 1 > 0, for any positive integer n, only one corrective addition with m m 3 is required to compute the modulo. ) (x 1 + ) is even and has the maximum possible value and x is zero. This is the largest positive value one may get and Equation (14) reduces to m (x 1 + ) m m 3. Given that m m 3 m (x 1 + ) 4n n (n)(n + n ) 4n n 4n + n 0 the maximum sum in the modulo adder cannot exceed m m 3, thus no correction is required. 3) (x 1 + ) 1 and x n 1. In this case Equation (15) reduces to m m 3 + m m 3x mm 3. Given that in this case m m 3 + m m 3x is always negative and that m m 3 + m m 3 + m m 3x n(n 1) + (n n) + n + (4n 4n + 1) n + n 1 > 0, only one corrective addition with m m 3 is required to compute the modulo. 4) (x 1 + ) odd has the maximum, possible value and x is zero. Equation (15) reduces to mm3 m + + (x 1 + ) m m 3. Given that m m 3 ( mm3 m (x 1 + )) (4n n) (n n + 4n n) 8n 4n 6n + 3n n n > 0 one corrective subtraction of m m 3 is required to compute the modulo.

6 The last elements on the critical path, a multiplier and an adder, have similar delays in both designs as they deal with operands within the same order of magnitude. Thus our proposal is certainly faster than the one in [1]. V. CONCLUSIONS In this paper, we investigated RNS to decimal conversion, which is an important issue concerning the utilization of RNS numbers in DSP applications. We presented a new algorithm for RNS to decimal conversion in the moduli set {n + 1, n, n 1}. First, we eliminated the computation of multiplicative inverses. Next, we further simplified the resulting CRT to obtain a low complexity implementation which does not require the explicit use of modulo operation in the conversion process as it is normally the case in the traditional CRT. The proposed converter operates on smaller numbers than other state of the art converters for the the same moduli set thus it requires less complex adders and multipliers. We demonstrated that from the algorithmic point of view the conversion process requires 3 or 4 additions and 4 multiplications thus its expected performance is similar to that of other state of the art equivalent converters. We also did a critical path analysis, which indicated that the proposed converter outperforms other state of the art converters in terms of speed at the expense of similar or lower area cost. [10].N.S. Swamy W. Wang and.o. Ahmad. oduli selection in rns for efficient vlsi implementation. International Symposium on Circuits and Systems, Vol. 4, pp , 003. [11] Y. Wang. New chinese remainder theorems. in Proc. Asilomar Conference, USA, pp , Nov., [1].O. Ahmad Y. Wang,.N.S. Swamy. Residue to binary number converters for three moduli set. IEEE Trans. Circuits Syst. II, vol. 46, pp , Feb., [13] H.. Yassine and W.R. oore. Improved mixed radix conversion for residue number system architectures. proceedings of IEEE pt-g, Vol. 138, No.1, pp.10-14, Feb., REFERENCES [1] W.K. Jenkins and B.J. Leon. The use of residue number systems in the design of finite impulse response digital filters. IEEE Trans. On circuitry and systems, vol. 4, pp , [] i Lu. Arithmetic and Logic in Computer Systems. John Wiley and Sons, New Jersey, 004. [3] G.A. Jullien.A. Soderstrand, W.K. Jenkins and F.J. Taylor. Residue Number Arithmetic: odern Application in Digital Signal Processing. IEEE press, New York, [4] B. Parhami. Arithmetic Algorithms and Hardware Designs. Oxford University Press, New York, 000. [5] A. B. Premkuma. An rns to binary converter in a three moduli set with common factors. IEEE Trans. on Circuits and Systems- II: Analog and Digital Processing, Vol. 4, No. 4, pp , April, [6] A. B. Premkuma. Corrections to an rns to binary converter in a three moduli set with common factors. IEEE Trans. on Circuits and Systems-II: Analog and Digital Processing, Vol. 51, No.1, pp 43, January, 004. [7] A. B. Premkumar. An rns to binary converter in n + 1,n, n 1 moduli set. IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 39, No. 7, pp , July, 199. [8] N. Szabo and R Tanaka. Residue Arithmetic and its Application to Computer Technology. C-Graw-Hill, New York, [9]. O. Ahmad W. Wang,.N.S. Swamy and Y. Wang. A study of the residue-to-binary converters for three-moduli sets. IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications, Vol. 50,No., Feb.,pp 35-43, 003.

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