CpE358/CS381. Switching Theory and Logical Design. Class 10


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1 CpE358/CS38 Switching Theory and Logical Design Class CpE358/CS38 Summer 24 Copyright
2 Today Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic (Ch ) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch ) Combinatoric logical design including LSI implementation (Chapter 4) Flipflops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata CpE358/CS38 Summer 24 Copyright
3 Course Roadmap Logic Circuits with gates CpE358/CS38 Summer 24 Copyright
4 Course Roadmap Combinatorial Circuits Logic Circuits with gates CpE358/CS38 Summer 24 Copyright
5 Course Roadmap Combinatorial Circuits Logic Circuits with gates Logic Circuits with memory CpE358/CS38 Summer 24 Copyright
6 Course Roadmap Combinatorial Circuits Logic Circuits with gates Sequential Circuits Logic Circuits with memory CpE358/CS38 Summer 24 Copyright
7 Course Roadmap Combinatorial Circuits Logic Circuits with gates Sequential Circuits Logic Circuits with memory Specific Specific functions CpE358/CS38 Summer 24 Copyright
8 Course Roadmap Combinatorial Circuits Logic Circuits with gates Sequential Circuits Logic Circuits with memory Specific Specific functions Registers and Counters CpE358/CS38 Summer 24 Copyright 2438
9 Shift Register S I D D D D D D D S O Clk Present Input Next Output S I S I S = 6 Nbit S/R S I S O SISO Register Serialin, Serialout CpE358/CS38 Summer 24 Copyright 2438
10 Shift Register Variants S I D D D D D D D S O Clk 2 N SIPO Register S I Nbit S/R S O Serialin, Parallelout CpE358/CS38 Summer 24 Copyright
11 Shift Register Variants D D D 2 2 D 3 3 D 4 4 D 5 5 D 6 6 D D D D D D D Clk D D D 2 D N Nbit S/R PIPO Register Parallelin, Parallelout 2 N CpE358/CS38 Summer 24 Copyright
12 Shift Register Variants D N2 D N N S I D D D S O Clk P/S D D D 2 D N P/S S I Nbit S/R S O Serial/Parallel Register Parallelin/Serialin, Parallelout/Serialout 2 N CpE358/CS38 Summer 24 Copyright
13 Tandem S/Rs Serial registers 2Nbit S/R S I Nbit S/R S O S I Nbit S/R S O CpE358/CS38 Summer 24 Copyright
14 Generic Moore Machine j Outputs m n B/ Transition Controls A/ C/ Inputs k All statetostate transitions are potentially allowable. CpE358/CS38 Summer 24 Copyright
15 S/Rbased Moore Machine S/R j Outputs n B/ Transition Controls A/ C/ Inputs k Only specific statetostate transitions are allowable. CpE358/CS38 Summer 24 Copyright
16 Shift Register Sequences Transition Controls Output Mapping S I I Nbit S/R S O CpE358/CS38 Summer 24 Copyright
17 Shift Register Sequences Input Transition Controls Output Mapping S I I Nbit S/R S O S I = ABCDE S I = BCDE BCDE S I = S I = S I = S I = BCD BCD BCD BCD CpE358/CS38 Summer 24 Copyright
18 S/R Data Scrambler/Encryptor Fracasi scrambler: S/R Sequential Function F(x) S/R Sequential Function F(x) Input Data + + Descrambled Data CpE358/CS38 Summer 24 Copyright 2439
19 S/R Data Scrambler/Encryptor Fraccassi scrambler: Nbit S/R Nbit S/R Nbit S/R Nbit S/R Nbit S/R Nbit S/R Input Data + + Descrambled Data CpE358/CS38 Summer 24 Copyright 2439
20 Course Roadmap Combinatorial Circuits Logic Circuits with gates Sequential Circuits Logic Circuits with memory Specific Specific functions Registers and Counters CpE358/CS38 Summer 24 Copyright
21 Generic Moore Machine j Outputs m n B/ Transition Controls A/ C/ Inputs k All statetostate transitions are potentially allowable. CpE358/CS38 Summer 24 Copyright
22 Counter Moore Machine Counter j Outputs m n B/ Transition Controls A/ C/ Inputs k tostate transitions follow a counting sequence Inputs (if any) may be used to set counting range, direction, starting point CpE358/CS38 Summer 24 Copyright
23 Counters Binary Ripple Counter J A K A CpE358/CS38 Summer 24 Copyright
24 Counters Binary Ripple Counter J A J B K K A B CpE358/CS38 Summer 24 Copyright
25 Counters Binary Ripple Counter J A B C J J K K K A B C CpE358/CS38 Summer 24 Copyright
26 Binary Ripple Counter (idealized) Counters J A B C J J K K K A B C CpE358/CS38 Summer 24 Copyright
27 Binary Ripple Counter (more realistic) Counters J A B C J J K K K A B C { { { { { { { CpE358/CS38 Summer 24 Copyright
28 Cascading Counters T CpE358/CS38 Summer 24 Copyright 244
29 Cascading Counters T T CpE358/CS38 Summer 24 Copyright 244
30 Cascading Counters T T T CpE358/CS38 Summer 24 Copyright 2442
31 Cascading Counters T T T T N CpE358/CS38 Summer 24 Copyright 2443
32 Cascading Counters T T T T N CpE358/CS38 Summer 24 Copyright 2444
33 Ripple Counters vs. Synchronous Counters F JAR (A,B,C) J A B C F JBR (A,B,C) J F JBR (A,B,C) J F KAR (A,B,C) K F KBR (A,B,C) K F KBR (A,B,C) K F JAS (A,B,C) J A B C F JBS (A,B,C) J F JBS (A,B,C) J F KAS (A,B,C) K F KBS (A,B,C) K F KBS (A,B,C) K CpE358/CS38 Summer 24 Copyright 2445
34 Synchronous Counters BCD Counter: table Present Next CpE358/CS38 Summer 24 Copyright 2446
35 Synchronous Counters BCD Counter: JK inputs BA DC BA DC J A K A J B K B Present Next J C J D K C K D JK operation: CpE358/CS38 Summer 24 Copyright 2447
36 J A J B J C J D BCD Counter: JK inputs BA DC CpE358/CS38 Summer 24 Synchronous Counters BA DC K A K B K C K D Copyright 24 JK operation: Present Next 48
37 J A J B J C J D BCD Counter: JK inputs BA DC CpE358/CS38 Summer 24 Synchronous Counters BA DC K A K B K C K D Copyright 24 JK operation: Present Next 49
38 J A J B J C J D BCD Counter: JK inputs BA DC CpE358/CS38 Summer 24 Synchronous Counters BA DC K A K B K C K D Copyright 24 JK operation: Present Next 4
39 J A J B J C J D BCD Counter: JK inputs BA DC CpE358/CS38 Summer 24 Synchronous Counters BA DC K A Copyright 24 K B J A = K A = J B = AD K C K B = A K D J C = AB K C = AB J D = ABC K D = A Present Next 4
40 Synchronous Counters BCD Counter J A B C J J J D K K K K J A = K A = J B = AD K B = A J C = AB K C = AB J D = ABC K D = A Present J D K D J C K C J B K B J A K A Next Present J D K D J C K C J B K B J A K A Next CpE358/CS38 Summer 24 Copyright 2442
41 Synchronous Counters BCD Counter Present J D K D J C K C J B K B J A K A Next Present J D K D J C K C J B K B J A K A Next CpE358/CS38 Summer 24 Copyright 2443
42 Varieties of Counters Counters with Parallel Load Normal counter operation Load C I D 3 D 2 D D Next C O D D D 2 D 3 C I C O LD 2 3 ABCD ABCD WYZ WYZ CpE358/CS38 Summer 24 Copyright 2444
43 Varieties of Counters Counters with Parallel Load Normal counter operation Load C I D 3 D 2 D D Next C O D D D 2 D 3 C I C O LD 2 3 ABCD ABCD WYZ WYZ CpE358/CS38 Summer 24 Copyright 2445
44 Varieties of Counters Counters with Parallel Load Loading next state in parallel Load C I D 3 D 2 D D Next C O D D D 2 D 3 = ABCD C I C O LD > ABCD ABCD ABCD WYZ WYZ CpE358/CS38 Summer 24 Copyright 2446
45 Varieties of Counters Counters with Parallel Load Load C I D 3 D 2 D D Next C O D D D 2 D 3 C I C O LD 2 3 ABCD ABCD WYZ WYZ CpE358/CS38 Summer 24 Copyright 2447
46 Varieties of Counters Counters with Parallel Load Load C I D 3 D 2 D D Next C O D D D 2 D 3 C I C O LD 2 3 ABCD ABCD WYZ WYZ CpE358/CS38 Summer 24 Copyright 2448
47 Cascading Synchronous Counters D D D 2 D 3 D D D 2 D 3 D D D 2 D 3 C I A C O LD C I C O B C LD LD C I C O A A 2A 3A C OA B CpE358/CS38 Summer 24 Copyright 2449
48 Programmable Synchronous Counters LSB D D D 2 D 3 D D D 2 D 3 MSB D D D 2 D 3 C I A C O LD C I B C O LD C I C C O LD Assume D 3C D A = b b b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b b Next C OA C OB C OC b b b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b b b b b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b b + ABCD EFGH ABCD EFGH+ ABCD ABCD+ b b b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b b CpE358/CS38 Summer 24 Copyright 2442
49 Applications of Programmable Counters Programmable divide by N frequency divider: 2 K N CI CO CI CI CO CI CO CI LD LD LD LD /N CpE358/CS38 Summer 24 Copyright 2442
50 Applications of Programmable Counters Reference Oscillator Voltage Divide Phase Lowpass Controlled f By K Comparator Filter R f R /K Oscillator f S Synthesized Frequency Phase Locked Loop f S /N Divide By N Channel Selection, N f S = N K f R PLL frequency synthesizers used in TV, radio, cellular phones, PCs, modems, etc. CpE358/CS38 Summer 24 Copyright
51 Applications of Programmable Counters Master f m Divide by f m /A A Divide by B f m /B Complex Digital System (e.g., PC) Divide by C f m /C CpE358/CS38 Summer 24 Copyright
52 Timing Signal Generation Master f m Phase A Phase B Complex Digital System (e.g., PC) Phase C CpE358/CS38 Summer 24 Copyright
53 Only FF is set at any given time Ring Counters s D D D D D A B C D E A B C D E CpE358/CS38 Summer 24 Copyright
54 Switchtail Ring Counters (Johnson Counter) A B C D D D D D A B C D E s D E CpE358/CS38 Summer 24 Copyright
55 Summary Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic (Ch ) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch ) Combinatoric logical design including LSI implementation (Chapter 4) Flipflops and state memory elements (Ch 5) Sequential logic analysis and design (Ch 5) Counters, shift register circuits (Ch 6) Hazards, Races, and time related issues in digital design (Ch 9) Synchronous vs. asynchronous design (Ch 9) Memory and Programmable logic (Ch 7) Minimization of sequential systems Introduction to Finite Automata CpE358/CS38 Summer 24 Copyright
56 Homework due in Class 2 Show all work Problems 6, 623, 629 CpE358/CS38 Summer 24 Copyright
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