Systems I: Computer Organization and Architecture


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1 Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flipflops. Each flipflop stores one bit of data; n flipflops are required to store n bits of data. There are several different types of registers available commercially. The simplest design is a register consisting only of flipflops, with no other gates in the circuit. Loading the register transfer of new data into the register. The flipflops share a common clock pulse (frequently using a buffer to reduce power requirements). Output could be sampled at any time. learing the flipflop (placing zeroes in all its bit) can be done through a special terminal on the flip flop.
2 4bit Register lock I A I A I 2 A 2 I 3 A 3 lear Registers With Parallel Load The clock usually provides a steady stream of pulses which are applied to all flipflops in the system. A separate control system is needed to determine when to load a particular register. The Register with Parallel Load has a separate load input. When it is cleared, the register receives it output as input. When it is set, it received the load input. 2
3 4bit Register With Parallel Load Load I A I A I 2 A 2 A 3 I 3 lock Shift Registers A shift register is a register which can shift its data in one or both directions. The simplest shift register simply connects the flipflops to their respective neighbor with the clock controlling the operation. If we wish to shift on some clock pulses but not others, we can inhibit the clock pulses on which we do not to shift. 3
4 4Bit Shift Register Serial Input Serial Output lock Serial Transfer A digital system is operating in a serial mode when information is transferred and manipulated one bit at a time, with bits transferred out of the source register into the destination register. This is different from parallel transfer where all the bits of a register are transferred at once. Serial transfer of information from register A to register B is done with shift registers, where the serial output from register A serves as the serial input for register B. 4
5 Serial Transfer From Register A to Register B SI Shift Register A SO SI Shift Register B SO L L lock Shift control lock Shift control L T T 2 T 3 T 4 Serial Transfer State Table Timing Pulse Initial value After T After T 2 After T 3 After T 4 Shift Register A Shift Register B 5
6 Serial Addition While operations are usually parallel because it is faster, serial operations require less equipment. Serial addition can demonstrate this point, allowing us to perform addition with a single full adder and our two addends stored in a pair of shift registers, with the carryout going into a type flipflop (and going back in as the carryin). Initially, register A and the carry flipflop are cleared to. The augend is initially placed in register B and serial addition is used to place it into register A. The sum is placed in shift register A, replacing the augend. Serial Adder Shift control L SI Shift Register A SO x y z FA S Serial input SI Shift Register B SO lear 6
7 Redesigning the Serial Adder We will use a pair of shift registers whose outputs will be x and y respectively. These are corresponding bits of the addends. S is the sum bit produced and a flipflop will hold the carry bit as the flipflop s state. We will implement it using a flipflop State Table for the Serial Adder Present State (t) Inputs Y Next State (t+) Output S Flipflop Inputs 7
8 arnaugh Map for xy = xy arnaugh Map for xy = x y = (x + y) 8
9 arnaugh Map for S xy S = x y Serial Adder Shift control L SI Shift Register A SO = x Serial input SI Shift Register B SO = y lear 9
10 Bidirectional Shift Registers A shift register that can shift in one direction is called a unidirectional shift register. A shift register that can shift in either direction is called a bidirectional shift register. Some shift register also allow for the simple transfer of data. General Shift Register The most general shift register have all of these capabilities: An input for clock pulses to synchronize all operations. A shiftright operation and serial line input line associated with the shiftright. A shiftleft operation and serial line input line associated with the shift left. A parallel load operation and n input lines associated with the parallel transfer. n parallel output lines. A control state that leaves the information in the register unchanged even though the clock pulses are applied.
11 Function Table For General Shift Register S S Register operation No change Shift Right (down) Shift Left (up) Parallel load Bidirectional Shift Register With Parallel Load I S S Serial Input S S 4 MU 2 3 A I S S 4 MU 2 3 A I 2 S S 4 MU 2 3 A 2 Serial Input I 3 lock S S 4 MU 2 3 A 3
12 ounters A register that goes through a prescribed sequences of states upon the application of an input pulse is called a counter. The input pulse may be a clock pulse or may have some other origin. A counter that goes through a binary sequence is called a binary counter. An nbit binary counter uses n flipflops and can count from to 2 n. Ripple ounters ounters are either ripple counters or synchronous counters. In synchronous counters, all flipflops receive the common clock pulse; therefore they change at the same time. In ripple counters, the output of one flipflop is used as a source for triggering others. 2
13 4Bit Ripple ounter Using TType Flipflop A 3 A 2 A A T R T R T R T R Logic Reset ount 4Bit Ripple ounter Using Type Flipflop A 3 A 2 A A R R R R Logic Reset ount 3
14 4 4Bit Ripple ounter Using Type Flipflop R A ount Reset R A R A 2 R A 3 Binary ount Sequence A A A 2 A 3
15 B Ripple ounter A binarycoded decimal ripple counter will return to after it reaches 9, this necessarily changes the logic Logic ount Threeecade B ounter B ounter B ounter B ounter ount pulse 2 digit digit digit 5
16 Binary ounters A counter is a register that goes through a predetermined sequence of states as input pulses are applied. Almost all digital equipment will contain counters; they are used for counting the occurrences of a particular event and are useful in generating timing signals. An nbit counter uses n flipflops and are have any value in the range to 2 n . We notice in our sequences that the lowest significance bit is complemented with every count and the other bits are complemented from one count to the next when all the lower bits are set. 4bit Synchronous Binary ounter ount Enable A A A 2 lock A 3 Output carry 6
17 Upown Binary ounter A countdown binary counter will go through binary states in reverse order. E.g., a 4bit countdown binary counter will start at, go to, then, and so on down to. As in regular counters, the least significant bit is always complemented. But higher bits are complemented only if the lower bits are all. We can design a counter that can go in either direction, depending on the control inputs. 4Bit Upown Binary ounter Up own T A T A T A 2 T A 3 lock 7
18 8 B ounter B counters only go through states to up to. The pattern is as regular as binary counter, so we must go through the design process. State Table for B ounter T T 2 T 4 T 8 y Present State Next State Output Flipflop Inputs
19 8 4 2 arnaugh Map For T 8 T 8 = arnaugh Map For T 4 T 4 = 2 9
20 8 4 2 arnaugh Map For T 2 T 2 = arnaugh Map For T T = 2
21 4Bit ounter With Parallel Load & Synchronous lear ounters often need to be preset with a prespecified value before counting begins. We also need the capability of clearing all bits simultaneously. Function Table For 4Bit Parallel Load ounter lock lear Load ount Operation No change Increment count Load inputs I through I 3 lear outputs 2
22 Load 4bit counter with parallel load & synchronous clear ount I A I A I 2 A 2 I 3 lock lear A 3 ounters With Unused States An nbit counter has 2n states, but there are occasions when we wish to use less than the total number of states available. The unused states may be treated as don tcare conditions (or assigned to specific next states). Because outside interference may land the counter in these states, we must ensure that the counter can find its way back to a valid state. 22
23 23 State Table For ounter With Unused States B B A A B A B A Next State Present State Flipflop Inputs arnaugh Maps for A and A B A B A A = B A = B
24 arnaugh Maps for B and B A B B = A B B = arnaugh Maps for and A B = B A B = 24
25 State iagram For ounter With Unused States Logic iagram For ounter With Unused States A B lock Logic 25
26 Ring ounter omputers need timing signals that indicate the sequence in which certain operations will take place. These can be generated by ring counters, circular shift registers with only one flipflop set at any time. The alternative to a 4bit ring counter is a 2bit counter that goes through 4 distinct states and uses a decoder. Ring ounter Vs. ounter and ecoder Shift right T T T 2 T 3 T T T 2 T 3 Ring counter (initial value = ) 2 x 4 decoder ount enable 2bit counter ounter and decoder 26
27 Sequence of Timing Signals From the Ring ounter L T T T 2 T 3 Switchtail Ring ounters Switchtail ring counter can double the number of states that a ring counter can provide. A B E A B E L 4stage switchtail ring counter 27
28 State Table For Switchtail ounter Flipflop Outputs Seq. Num. A B E AN gate required for output A E 2 AB 3 B 4 E 5 AE 6 A B 7 B 8 E ohnson ounters A A B B E E L Seq. #
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