Operating Manual Ver.1.1

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1 4 Bit Binary Ripple Counter (Up-Down Counter) Operating Manual Ver.1.1 An ISO 9001 : 2000 company , Electronic Complex Pardesipura, Indore , India Tel : /02, Fax: e mail : Website : Toll free :

2 Scientech Technologies Pvt. Ltd. 2

3 4 Bit Binary Ripple Counter (Up-Down Counter) DB14 Table of Contents 1. Introduction 4 2. Theory 5 3. Experiment 6 Study of 4 Bit Binary Ripple Counter Up counter Down counter 4. Data Sheet 9 5. Warranty List of Accessories 11 RoHS Compliance Scientech Products are RoHS Complied. RoHS Directive concerns with the restrictive use of Hazardous substances (Pb, Cd, Cr, Hg, Br compounds) in electric and electronic equipments. Scientech products are Lead Free and Environment Friendly. It is mandatory that service engineers use lead free solder wire and use the soldering irons upto (25 W) that reach a temperature of 450 C at the tip as the melting temperature of the unleaded solder is higher than the leaded solder. Scientech Technologies Pvt. Ltd. 3

4 Introduction DB14 is a compact, ready to use 4 Bit Binary Ripple Counter (Up-Down Counter) experiment board. This experiment board has been designed to study 4 Bit Binary Ripple Up/Down Counter and verify truth table. It can be used as stand alone unit with external power supply or can be used with Scientech Digital Lab ST2611 which has built in power supply, pulse generator, pulser switches, 8 bits data switches, logic probe, digital display, 8 bits LED display. List of boards : Model Name DB01 Logic Gates DB02 Universal Gate- NAND/NOR DB03 DB04 DB05 DB06 DB07 DB08 DB09 DB10 EX-OR Gate Implementation Demorgan's Theorem EX-OR Gate Application Code Conversion (Binary to Gray & Gray to Binary) Code Conversion (BCD to Excess-3 code) Binary Adder -Subtractor Encoder Decoder Multiplexer Demultiplexer DB11 Flip-Flops (R-S, D, J-K, T) DB12 DB13 DB16 DB15 DB17 DB21 DB22 DB27 DB28 DB29 DB30 DB31 DB32 DB35 Shift Register (4 bit SIPO) 4 Bit Synchronous Binary Counter Digital to Analog Converter (R-2R ladder) BCD to 7- Segment Decoder 3 Digit Event Counter Fiber Optic Digital Link Analog to digital converter (Counter Type) Digital to Analog Converter (R-2R ladder) Monostable Multivibrator CMOS and Crystal Oscillator Adder/ Subtracter (4-Bit/8-Bit) Decoder/Demultiplexer Modulo-N programmable counter 4 BIT Shift Register and many more Scientech Technologies Pvt. Ltd. 4

5 Theory A sequential circuit that goes through a prescribed sequence of states upon the application of input pulses is called a counter. A counter that follows the binary sequence is called a binary counter. An n-bit binary counter consists of n flip-flops and can count in binary from 0 to 2 n -1. State transitions in clocked sequential circuits occur during a clock pulse; the flip-flops remain in their present states if no pulse occurs. Counters come in two categories: 1. Ripple counters 2. Synchronous counters. In a ripple counter, the flip-flop output transition serves as a source (i.e clock) for triggering other flip-flops. i.e. CP inputs of all flip-flops (except the first) are triggered not by the incoming pulses but rather by transition that occurs in other flip-flops. In a synchronous counter, the input pulses are applied to all CP inputs of flip-flops. 4 Bit Synchronous Binary Up Counter : Observe truth table of 4 bit synchronous binary UP counter as shown in figure 1, the flip-flop in the lowest-order position is complemented with every pulse so J and K inputs must be maintained at logic-1. A flip-flop in any other position is complemented with a pulse provided all the bits in the lower-order position are equal to 1, because the lower-order bits (when all ones) will change to 0's on the next count pulse. Refer truth table. The binary count dictates that the next higher-order bit be complemented. If the present state of a 4-bit counter is Q 3 Q 2 Q 1 Q 0 = 0011, the next count will be Q 0 is always complemented. Q 1 is complemented because the present state of Q 0 = 1. Q 2 is complemented because the present state of Q 1 Q 0 = 11 but Q 3 is not complemented because the present state of Q 2 Q 1 Q 0 = 011, which does not give an all 1 s condition. The CP terminal of all flip-flops is connected to a common clock pulse source. The first stage Q 0 has its J and K equal to 1. The other J and K inputs are equal to 1 if all previous low order bits are equal to 1 and the count is enabled. The chain of AND gates generate the required logic for the J and K inputs in each stage. As shown in figure MS is master set input which sets output of flipflops to logic 1, when connected to logic 0. MC D is master reset input which resets or clears output when connected to logic 0. Q 3 Q 2 Q 1 Q 0 are outputs of flip-flops where Q 0 is LSB.CP is clock pulse input. It will trigger flip-flops on negative edge i.e +5 V to 0 transition (1 0). Scientech Technologies Pvt. Ltd. 5

6 Experiment Objective : Study of 4 Bit Synchronous Binary Up Counter Equipments Needed : 1. Digital board DB13 2. DC Power Supply +5V from external source or ST2611 Digital Lab. 3. Oscilloscope, Digital Multimeter or Digital Lab ST2611. Logic Diagram & Truth Table : (Logic 1 = +5V & Logic 0= GND) 4- Bit Synchronous Binary up Counter Figure 1 Scientech Technologies Pvt. Ltd. 6

7 v S. no. MS MC D CP Q3 Q2 Q1 Q Q 0 is LSB Table 1 Scientech Technologies Pvt. Ltd. 7

8 Procedure : Connect +5 V and ground to their indicated position on DB13 experiment board from external DC power supply or from DC power block of Digital Lab ST Switch On the power supply. 2. Connect logic 1(+5 V) to CP and MS input. 3. Clear the outputs Q0-Q3 by Connecting logic 0 (Gnd or 0V) to MC D input of 4 bit synchronous counter of figure 1 as per truth table. 4. Observe output on multimeter or on LED display of Digital Lab ST2611. It will be Connect logic 1 to MC D and MS inputs. 6. Connect logic 1 to MC D input. 7. Observe output on multimeter or on LED display of of Digital Lab ST2611. It will be Connect logic 0 to CP input. 9. Observe output on multimeter or on LED display of of Digital Lab ST2611. It will be Make CP terminal to transit from 1 to 0 (1 0) and observe next state of counter as shown in truth table for counter and prove truth table. 11. Repeat step 10 until last state 1111 appear. Scientech Technologies Pvt. Ltd. 8

9 Data Sheet General Description : The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT08 provide the 2-input AND function. Note : 1. H = High Voltage Level 2. L = Low Voltage Level Scientech Technologies Pvt. Ltd. 9

10 Dual J K Flip Flop 7476 Note : Pull up resistance of 1 K is required in open collector ICs to get output. Scientech Technologies Pvt. Ltd. 10

11 Warranty 1. We guarantee the product against all manufacturing defects for 24 months from the date of sale by us or through our dealers. Consumables like dry cell etc. are not covered under warranty. 2. The guarantee will become void, if a) The product is not operated as per the instruction given in the operating manual. b) The agreed payment terms and other conditions of sale are not followed. c) The customer resells the instrument to another party. d) Any attempt is made to service and modify the instrument. 3. The non-working of the product is to be communicated to us immediately giving full details of the complaints and defects noticed specifically mentioning the type, serial number of the product and date of purchase etc. 4. The repair work will be carried out, provided the product is dispatched securely packed and insured. The transportation charges shall be borne by the customer. For any Technical Problem Please Contact us at List of Accessories 1. 2 mm. Patch Cord (Red) No mm Patch Cord (Black) No mm Patch Cord (Blue) Nos. 4. e-manual...1 No. Updated Scientech Technologies Pvt. Ltd. 11

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