Memory Elements. Combinational logic cannot remember


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1 Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic circuits to hold (remember) logic values 2 basic types of memory elements Latches Levelsensitive to inputs Flipflops Edgetriggered on active edge of clock C. E. Stroud Latches & Flipflops (10/12) 1
2 ResetSet (RS) Latch (NOR) The simplest memory element Aka setreset (SR) latch Crosscoupled NOR gates Level sensitive S Active high inputs R (reset) S (set) Only one input can be active To avoid undefined state Outputs: and = current state of latch R R S Function 0 0 Storage Set Reset ? 0? Undefined C. E. Stroud Latches & Flipflops (10/12) 2
3 ResetSet (RS) Latch (NAND) Dual of NOR RS latch Crosscoupled NAND gates Level sensitive Active low inputs R (reset) S (set) Only one input can be active To avoid undefined state Outputs: and = current state of latch R S R S Function ? 1? Undefined Reset Set 1 1 Storage C. E. Stroud Latches & Flipflops (10/12) 3
4 Enabled ResetSet (RS) Latch (NOR) Aka gated RS latch When enable E is inactive, RS latch is forced into storage state R and S can do nothing AND gates plus NOR RS latch Level sensitive Active high inputs E (enable) R (reset) S (set) R and S cannot both be active when E is active To avoid undefined state Outputs: and = current state of latch E R S Function 0 X X Storage Storage Set Reset ? 0? Undefined C. E. Stroud Latches & Flipflops (10/12) 4 R E S
5 Enabled ResetSet (RS) Latch (NAND) Aka gated RS latch When enable E is inactive, RS latch is forced into storage state R and S can do nothing OR gates plus NAND RS latch Level sensitive Active low inputs E (enable) R (reset) S (set) R and S cannot both be active when E is active To avoid undefined state Outputs: and = current state of latch E R S Function 1 X X Storage ? 1? Undefined Reset Set Storage C. E. Stroud Latches & Flipflops (10/12) 5 R E S
6 Enabled Data or Delay (D) Latch Aka transparent D latch Overcomes undefined state R & S never active at same time Inverter plus enabled RS latch D E Level sensitive Active high enable for NOR latch Active low enable for NAND latch E D Function 0 X Storage Transparent Transparent C. E. Stroud Latches & Flipflops (10/12) 6 D E E D Function Transparent Transparent 1 X Storage logic symbols D active low E D active high E
7 D FlipFlop Aka MasterSlave flipflop Two transparent D latches Sensitive to opposite levels of Clock master One is always in storage and the other master transparent transparent slave storage Edgetriggered D D active low E Clock Data moves through on Clock transition Activelow latch followed by activehigh D D active Rising edgetriggered high aka leading edgetriggered E Activehigh latch followed by activelow master Falling edgetriggered master transparent aka trailing edgetriggered slave storage Clock D active high E slave D active low E master storage slave transparent rising edge slave master storage slave transparent falling edge C. E. Stroud Latches & Flipflops (10/12) 7
8 D FlipFlop Gatelevel implementation No need for inverter in slave latch since master has & D activelow activehigh Rising edgetriggered D flipflop D activehigh activelow Falling edgetriggered D flipflop C. E. Stroud Latches & Flipflops (10/12)
9 Timing Considerations Setup time (t su ) = minimum time data (D) must be valid at input to flipflop prior to the active edge of the clock Hold time (t h ) = minimum time data (D) must remain valid at input to flipflop after the active edge of the clock Clocktooutput delay (t co ) = maximum time before output data () is valid after the active edge of the clock D t su t h t co C. E. Stroud Latches & Flipflops (10/12) 9
10 Timing Considerations Setup & hold time violations in a real circuit result in metastability Flipflop goes to intermediate logic levels ( = ) Eventually resolves to an unknown state Setup & hold time violations in a vector set for simulation referred to as clockdataraces Leads to invalid simulation results & manufacturing testing problems C. E. Stroud Latches & Flipflops (10/12) 10 D t su t h t co
11 What is the Clock? Typically a periodic signal (a sequence of pulses) used to: sample data, and store the sampled data in memory elements Clock frequency = 1/period f clk = 1/T p T p t co + P del + t su t co time for P del t su 1 P del T p  t co  t su period T p time 0 C. E. Stroud Latches & Flipflops (10/12) 11
12 Serial Shift Register Example A series of D flipflops whose outputs are connected to the input of the next flipflop serialin, serialout = data in on Din, data out on c serialin, parallelout = data in on Din, data out on a, b, and c Din a b c time Timing diagram Din a b c C. E. Stroud Latches & Flipflops (10/12) 12
13 Another Shift Register Example A series of multiplexers and D flipflops whose outputs are connected to the input of the next flipflop parallelin, parallelout = data in on Da, Db, and Dc; data out on a, b, and c (Shift/Load = 0) parallelin, serialout = data in on Da, Db, and Dc; data out on c (Shift/Load = 0, then Shift/Load = 1) Serialin, serialout = data in on Din, data out on c (Shift/Load = 1) Serialin, parallelout = data in on Din, data out on a, b, and c (Shift/Load = 1) Da Db Dc Din Shift/Load a b c C. E. Stroud Latches & Flipflops (10/12) 13
14 PSIM Architecture Sequential Logic: Program Memory (MEM) Program Counter (PC) Address Register (AR) Data Register (DR) Input Register (IN) Output Register (OR) Accumulator (AC) ALU Carry Register (C) Instruction Register (IR) Timing Counter (TC) Combinational Logic: Control Logic Arithmetic/Logic Unit (ALU) Multiplexers 1&2 (MUX) C. E. Stroud Latches & Flipflops (10/12) 14
15 Another Register Example A series of multiplexers and D flipflops whose outputs are connected to the input of the MUX Register with active high Load Load = 1 & rising edge of clock: parallelin, parallelout = data in on Da, Db, and Dc; data out on a, b, and c Otherwise: Holds data; data out remains on a, b, and c Basic register design used in PSIM for: AR, DR, OR, IN (all bits) and IR (4bits) Da Db Dc Load a C. E. Stroud Latches & Flipflops (10/12) 15 b c
16 Accumulator Register Example Accumulator in PSIM Functions controlled by combinational logic design Including holding data when no operations are specified Via feedback of AC i Only need a flipflop at output of MUX AC register (bits) C register (1bit) Similar to AC i design shown here ACC2 DR i AC i ACC1 AC i DR i 3 AC_C20 C. E. Stroud Latches & Flipflops (10/12) 16 Cin adder AC i Sum i AC i DR i AC i DR i Clock AC i DR i Z i AC i
17 Random Access Memory (RAM) Assuming MEM from PSIM bit address => 256 words MADD bit words Input data = bits From DR Output data = bits From MEM Active high write enable WRMEM When WRMEM = 1, data from DR is written into address location specified by MADD MADD(70) WRMEM ADD WE DR(70) DIN MEM DOUT MEM(70) (to DR) C. E. Stroud Latches & Flipflops (10/12) 17
18 RAM continued RAM consists of: Address decoder with enable Produces active high enables to registers Registers with parallel load Stores data associated with specified address Read MUX Reads specified address ADD(70) WR DECODE W 0 W 255 DIN DI LD Word 0 DO DI LD Word 255 DO ADD(70) MUX DOUT C. E. Stroud Latches & Flipflops (10/12) 1
19 RAM continued Word Registers with parallel load Dlatches with active high enable W i DIN DI LD Word 0 DO WORD i DI 0 DI 7 D LD i D active high E D active high E E DO 0 DO 7 C. E. Stroud Latches & Flipflops (10/12) 19
20 RAM continued Read MUX Word 0 MUX DOUT 256to1 MUXs Word 255 Functional equivalent Address decoder input AND gates inverters ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 ADD6 ADD7 Word 0 B i ADD(70) example DOUT i ADD0 W ADD0 0 ADD1 ADD1 ADD2 ADD2 example ADD3 ADD3 ADD4 W 12 ADD4 ADD5 ADD5 WR W ADD6 ADD6 255 ADD7 ADD7 WR Word 255 B i C. E. Stroud Latches & Flipflops (10/12) 20 ADD(70) DECODE
21 What is Sequential Logic? A collection of logic gates and flipflops The logic values stored in the flipflops establish the current state of the sequential logic circuit The logic values at the inputs in conjunction with the current state determines the next state of the sequential logic circuit after the active edge of the clock Primary Inputs Current State Comb Logic Flip Flips Next State Primary Outputs generalized architecture for sequential logic circuits also known as Huffman model C. E. Stroud Latches & Flipflops (10/12) 21
22 FlipFlop Information for Sequential Logic Design Types of flipflops D (data) T (toggle) SR (setreset) Also known as RS (resetset) JK (Jack Kilby) We will consider only edgetriggered flipflops Each type has associated: Characteristic equation Characteristic table sometimes called state table State diagram Excitation table All provide same basic information but in slightly different forms C. E. Stroud Latches & Flipflops (10/12) 22
23 State Diagrams & State Tables Describe complete operation of sequential logic circuit Vertices (nodes) represent states Edges represent state transitions on active edge of clock based on primary input logic values State diagram & state tables provide exact same information Diagram is graphical representation of same info as in state table Given current state and primary input values we can determine the next state after active edge of clock C. E. Stroud Latches & Flipflops (10/12) 23
24 D FlipFlop Specification state diagram 1 characteristic equation + = D characteristic table D D logic diagram excitation table + D C. E. Stroud Latches & Flipflops (10/12) 24
25 T FlipFlop Specification state diagram characteristic table T + Mode 0 Storage 1 Toggle 0 T characteristic equation + = T + T = T logic diagram excitation table + T C. E. Stroud Latches & Flipflops (10/12) 25
26 RS FlipFlop Specification state diagram 10 0X 0 1 X0 01 input ordering = SR characteristic table S R + Mode 0 0 Storage Reset Set 1 1? Indeterminant R S logic diagram characteristic equation + = S + R excitation table + SR 0 0 0X X0 C. E. Stroud Latches & Flipflops (10/12) 26
27 JK FlipFlop Specification state diagram 1X 0X 0 1 X0 X1 input ordering = JK characteristic table J K + Mode 0 0 Storage Reset Set 1 1 Toggle J K logic diagram characteristic equation + = J + K excitation table + JK 0 0 0X 0 1 1X 1 0 X1 1 1 X0 C. E. Stroud Latches & Flipflops (10/12) 27
28 FlipFlop Initialization Preset (aka set) => + = 1 Clear (aka reset) => + = 0 Some flipflops have: Both preset and clear (set and reset) A preset or a clear Neither (JK & SR flops have set/reset functions) Preset and/or clear can be Active high or active low Typical logic symbol with active high preset and active low clear Cannot determine sync or async from symbol Synchronous => with respect to active edge of clock Asynchronous => independent of clock edges Initialization important for: logic simulation to remove undefined logic values (2, 3, U, etc.) system operation to put system in a known state C. E. Stroud Latches & Flipflops (10/12) 2 D Pre Clr
29 Synchronous vs. Asynchronous Synchronous => states of memory elements change only with respect to active edge of clock Asynchronous => states of memory elements can change without an active edge of clock Asynchronous designs often have timing problems Example: assume sync preset and async clear D Pre Clr D Pre Clr C. E. Stroud Latches & Flipflops (10/12) 29
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