Digital Logic Design Sequential circuits
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1 Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian Dr. Eng. Rania.Swief Dr. Eng. Ahmed H. Madian
2 Registers An n-bit register consists of a group n flip - flops capable of storing n bits of binary info. All Flip-flops are connected to one clock source Each flip-flop can store one bit of Info. Clear signal during normal operation is set to high The clear input is useful for clearing all the content of the register to all 0 s Problem: Typically don t want to load every clock Solution: use a external signal to control the operation of the load Dr. Eng. Ahmed H. Madian 2
3 Registers with Parallel Load Dr. Eng. Ahmed H. Madian 3
4 Shift Registers A register capable of shifting its binary information in one or both direction is called a shift register A chain of flip-flops connected in cascade 00 0 Qa Qb Qc SI CLK Qa Qb etc Dr. Eng. Ahmed H. Madian 4
5 Universal Shift Registers No Change Shift Right Shift Left Parallel Load Need a Clear and Clock S S2 Action 0 0 No Change 0 Shift Right 0 Shift Left Parallel Load Dr. Eng. Ahmed H. Madian 5
6 Basic Sequential Circuits Ripple Counters. Synchronous Counters. Counters with Unused States. Up/Down Counters Dr. Eng. Ahmed H. Madian 6
7 Counters A counter is a register that goes through a predetermined sequence of stat es upon the application of clock pulses. Counters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle. After the largest value, the output wraps around back to 0. Counters could be implemented with flip-flops (JK-, D-, T-FFs) current state next state bit up-counter Dr. Eng. Ahmed H. Madian 7
8 Counters Dr. Eng. Ahmed H. Madian 8
9 JK (or T) Flip flop A JK( or T) flip flop toggles when both inputs are. In this case it effectively counts every second clock pulse: clock J Q K ~Q clock Q You can also say it counts from 0 to and back again. Sometimes called a scale of 2 counter Dr. Eng. Ahmed H. Madian 9
10 Counter Connect two such flip flops together: Q Q2 clock Complete the timing diagram for Q2 clock Q Q2 Q2Q: Dr. Eng. Ahmed H. Madian 0
11 Counter (From D-FF) CLK A 0 D Flip-Flop Frequency Divider Dr. Eng. Ahmed H. Madian
12 4-bit Ripple counter (Asynchronous) e.g. A 4 bit ripple counter using negative edge triggered T and D FFs Asynchronous means each flip flop is triggered by the preceding one. Negative edge Trigger A to toggle Dr. Eng. Ahmed H. Madian 2
13 BCD Ripple counter Dr. Eng. Ahmed H. Madian 3
14 Counters Synchronous counters Outputs of all the flipflops change at the same time e.g. a 2-bit synchronous counter clk J K Q Q Q a J K Q Q Q b C 0 Q a 0 Q b Dr. Eng. Ahmed H. Madian
15 Synchronous counter using (JK-FF) All flip-flops driven with the same clock If count enable = the count begins The flip-flop of the least significant position (ex. A 0 ) is complemented with every pulse Other flip-flops is complemented when all the bits in the lower position is equal Dr. Eng. Ahmed H. Madian 5
16 Unused states The examples shown so far have all had 2 n states, and used n flipflops. But sometimes you may have unused, leftover states For example, here is a state table and diagram for a counter that repeatedly counts from 0 (000) to 5 (0). What should we put in the table for the two unused states? Present State Next State Q 2 Q Q 0 Q 2 Q Q ?????? /27/20 6 Dr. Eng. Ahmed H. Madian 03 6
17 Unused states can be don t cares To get the simplest possible circuit, you can fill in don t cares for the next states. This will also result in don t cares for the flip-flop inputs, which can simplify the hardware. If the circuit somehow ends up in one of the unused states (0 or ), its behavior will depend on exactly what the don t cares were filled in with. Present State Next State 000 Q 2 Q Q 0 Q 2 Q Q x x x x x x Dr. Eng. Ahmed H. Madian 7
18 or maybe you do care To get the safest possible circuit, you can explicitly fill in next states for the unused states 0 and. This guarantees that even if the circuit somehow enters an unused state, it will eventually end up in a valid state. This is called a self-starting counter. Present State Next State Q 2 Q Q 0 Q 2 Q Q Dr. Eng. Ahmed H. Madian 8
19 Example Design a 3-bit counter synchronous that could count up or down directions using one control signal Down If Down = it counts down from ( to 000) If Down = 0 it counts up from (000 to ) Dr. Eng. Ahmed H. Madian 9
20 Up-Down Counter state diagram bit up-down counter 00 Down = > -> 0 -> 0 ->.. Dr. Eng. Ahmed H. Madian 20
21 Up-Down Counter (From D-FF) Present State Next State Q2(t) Q(t) Q0(t) Q2(t+) Q(t+) Q0(t+) Dr. Eng. Ahmed H. Madian 2
22 D-FF easiest to use 0 Q2 Up-Down Counter (From D-FF) 00 0 Q0 0 Q K-map for D D = Q 0 Q + Q 0 Q Q Q0 0 Q K-map for D2 D 2 = Q 2 Q 0 + Q Q 2 +Q 0 Q Q 2 Dr. Eng. Ahmed H. Madian 22
23 Up-Down Counter (From T-FF) Present State Next State T-FF Input Q2(t) Q(t) Q0(t) Q2(t+) Q(t+) Q0(t+) T2 T T Dr. Eng. Ahmed H. Madian 23
24 D-FF easiest to use Up-Down Counter (From T-FF) T0 = T = Q0 Q Q0 0 Q K-map for T2 T2 =Q0 Q Dr. Eng. Ahmed H. Madian 24
25 Up-Down Counter (From T-FF) Dr. Eng. Ahmed H. Madian 25
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