Chapter 8. Sequential Circuits for Registers and Counters
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1 Chapter 8 Sequential Circuits for Registers and Counters
2 Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
3 Outline Counters T-FF Basic Counting element State Diagram of -ve Pulse triggered 16-state counter Ripple Counter Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
4 Counting Often there is a need to count the number of pulses or triggering at an input. Counting is an essential circuit in computers. Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
5 Various Features in counters Delays at FFs Synchronous and Ripple Output bits at FFs 4, 8 or 16 bit FFs used D-FF, JK, RS Family TTL, LSTTL, CMOS, HCMOS Outputs Synchronous, Asynchronous Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
6 Modulo-6 Counter If a counter returns to original state after Q B = 1, Q C = 0 and Q D = 1, and Q A is always = 0 we say it is modulo-6 counter Counter returns to original state of Qs after 6 counts Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
7 State Diagram of Modulo 7 S 0 S 1 S S 4 1 S 5 1 Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
8 Modulo-7 Counter If a counter returns to original state after Q B = 1, Q C = 1 and Q D = 0, and Q A is always = 0, we say it is modulo-7 counter Counter returns to original state of Qs after 7 counts Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
9 State Diagram of Modulo 7 S 0 S 1 S S 6 1 Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
10 Modulo-10 Counter If a counter returns to original state after Q A = 1, Q B = 0 Q C = 0 and Q D = 1, we say it is modulo-10 counter Counter returns to original state of Qs after 10 counts Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
11 State Diagram of Modulo 10 S 0 S 1 S S 9 1 S 7 1 Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
12 Various types of counters Ripple Counter 4, 8 or 16 bit Binary Counter 4, 8 or 16 bit Ring Counter 4, 8 or 16 bit Decade Counter - Modulo 10 Modulo n counter 5, 10 or 6 bit Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
13 Outline Counters T-FF Basic Counting element State Diagram of -ve Pulse triggered 16-state counter Ripple Counter Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
14 Divide by 2 as Counting Element A divide-by-2 circuit produces one output pulse for every two pulses applied to its input. A divide-by-two circuit is made from a T-FF Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
15 T and JK FFs for Counting 1. Use a circuit of T-type flip-flop 2. Use a single JK flip-flop with its J and K inputs made 1. The T-flip-flop (FF) is designed from JK or any other method to act as a divide-by-two circuit and JK input is now the T-input. Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
16 TD and SR FFs for Counting 3.Use a D flip-flop (not D-latch) with its Q output feedback to the D input 4. Alternatively Use a S-R flip-flop with a NOT in-between S and R to get a D-FF and then convert a D-FF into T Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
17 T-FF D input = T XOR Q n and Q n+1 = Q n JK FF functions as T-FF if J = 1 and K =1 Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
18 T- from D- Flip-Flop + ve edge Output Q and Q triggered D Q T +ve Edge triggered circuit T D Divide by 2 FF Q Q Q Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
19 T from JK Flip-Flop ve edge Output Q and Q T -ve Edge triggered circuit J = 1 K=1 triggered clear R S Preset 1 Clock 1 PR Divide by 2FF Q Q Q Q CLR Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
20 Outline Counters T-FF Basic Counting element State Diagram of -ve Pulse triggered 16-state counter Ripple Counter Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
21 State Diagram S 15 1 S 0 S S 11 1 S 7 1 Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
22 Outline Counters T-FF Basic Counting element State Diagram of -ve Pulse triggered 16-state counter Ripple Counter Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
23 Cascading T-FFs T FF acts as a divide-by-2 circuit, if Q output of the FF connects to the T input of the second FF, and the Q output from the second FF connects to T-input of the third flip-flop and so on, the FFs are said to be in a cascade Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
24 4-bit Ripple Counter (Binary Asynchronous Counter) Count input A After t p After 4 t p Divide by 2FF Q input B Divide by 2FF Q Divide by 2FF QDivide by 2FF Q Q Q CLR Asynchronous Counter as each flip flop has output delay t p of s and final output delays by 4 times the t p of one FF Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
25 Additional feature in ripple counter in IC 7493 to enable its conversion to modulo-6 counter R (1) R (2) To CLR Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
26 -ve edge triggered T- FF Inputs CLR = 1, J = K = 1 CLR = 1, J = K = 1 Outputs CLK Count= Q n+1(a) Q n+1(b) Q n+1(c) Q n+1(d) Q n+1 means next state after n th clock input and after a delay of t p at successive FFs. At each transition, Delay = 4 t p at Q n+1(d) Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
27 -ve edge triggered T- FF Inputs CLR = 1, J = K = 1 CLR = 1, J = K = 1 Outputs CLK Count = Q n+1(a) Q n+1(b) Q n+1(c) Q n+1(d) Q n+1 means next state after n th clock input and after a delay of t p at successive FFs. Delay = 4 t p at Q n+1(d) on each transition Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
28 Timing Diagram when -ve edge asynchronous counter QD delays transition by 4 tp from clock edge CLK (shift) Q A Q B Q C Q D t Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
29 Summary Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
30 Counters T-FF functions as counter, because it toggles at every negative edge T-FF is made from J-K, D-FF when D = Q and from RS-FF, when S = R and S connects Q Ripple counter has cascaded T-FFs, the output of each FF connects to T-input of the next Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
31 Counters Counting delay = n times t p for a n-bit ripple counter 16-bit can be converted to modulo-6, 7 and 10 counters by resetting the counter at next transition when Qs show count = 5, 6 and 9 Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
32 End of Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
33 THANK YOU Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education,
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74LS193 Synchronous 4-Bit Binary Counter with Dual Clock
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54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control
54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous
Upon completion of unit 1.1, students will be able to
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NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6
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Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description
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Experiment No. 1. THE DIGI DESIGNER Experiment 1-1. Socket Connections on the Digi Designer Experiment No. 2. LOGIC LEVELS AND THE 7400 QUADRUPLE 2-INPUT POSITIVE NAND GATE Experiment 2-1. Truth Table
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