Chapter 8. Sequential Circuits for Registers and Counters


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1 Chapter 8 Sequential Circuits for Registers and Counters
2 Lesson 3 COUNTERS Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
3 Outline Counters TFF Basic Counting element State Diagram of ve Pulse triggered 16state counter Ripple Counter Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
4 Counting Often there is a need to count the number of pulses or triggering at an input. Counting is an essential circuit in computers. Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
5 Various Features in counters Delays at FFs Synchronous and Ripple Output bits at FFs 4, 8 or 16 bit FFs used DFF, JK, RS Family TTL, LSTTL, CMOS, HCMOS Outputs Synchronous, Asynchronous Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
6 Modulo6 Counter If a counter returns to original state after Q B = 1, Q C = 0 and Q D = 1, and Q A is always = 0 we say it is modulo6 counter Counter returns to original state of Qs after 6 counts Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
7 State Diagram of Modulo 7 S 0 S 1 S S 4 1 S 5 1 Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
8 Modulo7 Counter If a counter returns to original state after Q B = 1, Q C = 1 and Q D = 0, and Q A is always = 0, we say it is modulo7 counter Counter returns to original state of Qs after 7 counts Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
9 State Diagram of Modulo 7 S 0 S 1 S S 6 1 Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
10 Modulo10 Counter If a counter returns to original state after Q A = 1, Q B = 0 Q C = 0 and Q D = 1, we say it is modulo10 counter Counter returns to original state of Qs after 10 counts Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
11 State Diagram of Modulo 10 S 0 S 1 S S 9 1 S 7 1 Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
12 Various types of counters Ripple Counter 4, 8 or 16 bit Binary Counter 4, 8 or 16 bit Ring Counter 4, 8 or 16 bit Decade Counter  Modulo 10 Modulo n counter 5, 10 or 6 bit Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
13 Outline Counters TFF Basic Counting element State Diagram of ve Pulse triggered 16state counter Ripple Counter Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
14 Divide by 2 as Counting Element A divideby2 circuit produces one output pulse for every two pulses applied to its input. A dividebytwo circuit is made from a TFF Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
15 T and JK FFs for Counting 1. Use a circuit of Ttype flipflop 2. Use a single JK flipflop with its J and K inputs made 1. The Tflipflop (FF) is designed from JK or any other method to act as a dividebytwo circuit and JK input is now the Tinput. Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
16 TD and SR FFs for Counting 3.Use a D flipflop (not Dlatch) with its Q output feedback to the D input 4. Alternatively Use a SR flipflop with a NOT inbetween S and R to get a DFF and then convert a DFF into T Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
17 TFF D input = T XOR Q n and Q n+1 = Q n JK FF functions as TFF if J = 1 and K =1 Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
18 T from D FlipFlop + ve edge Output Q and Q triggered D Q T +ve Edge triggered circuit T D Divide by 2 FF Q Q Q Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
19 T from JK FlipFlop ve edge Output Q and Q T ve Edge triggered circuit J = 1 K=1 triggered clear R S Preset 1 Clock 1 PR Divide by 2FF Q Q Q Q CLR Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
20 Outline Counters TFF Basic Counting element State Diagram of ve Pulse triggered 16state counter Ripple Counter Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
21 State Diagram S 15 1 S 0 S S 11 1 S 7 1 Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
22 Outline Counters TFF Basic Counting element State Diagram of ve Pulse triggered 16state counter Ripple Counter Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
23 Cascading TFFs T FF acts as a divideby2 circuit, if Q output of the FF connects to the T input of the second FF, and the Q output from the second FF connects to Tinput of the third flipflop and so on, the FFs are said to be in a cascade Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
24 4bit Ripple Counter (Binary Asynchronous Counter) Count input A After t p After 4 t p Divide by 2FF Q input B Divide by 2FF Q Divide by 2FF QDivide by 2FF Q Q Q CLR Asynchronous Counter as each flip flop has output delay t p of s and final output delays by 4 times the t p of one FF Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
25 Additional feature in ripple counter in IC 7493 to enable its conversion to modulo6 counter R (1) R (2) To CLR Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
26 ve edge triggered T FF Inputs CLR = 1, J = K = 1 CLR = 1, J = K = 1 Outputs CLK Count= Q n+1(a) Q n+1(b) Q n+1(c) Q n+1(d) Q n+1 means next state after n th clock input and after a delay of t p at successive FFs. At each transition, Delay = 4 t p at Q n+1(d) Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
27 ve edge triggered T FF Inputs CLR = 1, J = K = 1 CLR = 1, J = K = 1 Outputs CLK Count = Q n+1(a) Q n+1(b) Q n+1(c) Q n+1(d) Q n+1 means next state after n th clock input and after a delay of t p at successive FFs. Delay = 4 t p at Q n+1(d) on each transition Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
28 Timing Diagram when ve edge asynchronous counter QD delays transition by 4 tp from clock edge CLK (shift) Q A Q B Q C Q D t Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
29 Summary Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
30 Counters TFF functions as counter, because it toggles at every negative edge TFF is made from JK, DFF when D = Q and from RSFF, when S = R and S connects Q Ripple counter has cascaded TFFs, the output of each FF connects to Tinput of the next Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
31 Counters Counting delay = n times t p for a nbit ripple counter 16bit can be converted to modulo6, 7 and 10 counters by resetting the counter at next transition when Qs show count = 5, 6 and 9 Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
32 End of Lesson 3 COUNTERS Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
33 THANK YOU Ch16L3 "Digital Principles and Design", Raj Kamal, Pearson Education,
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