# Fig1-1 2-bit asynchronous counter

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1 Digital electronics 1-Sequential circuit counters Such a group of flip- flops is a counter. The number of flip-flops used and the way in which they are connected determine the number of states and also the specific sequence of states that the counter goes through during each complete cycle. Counters are classified according to the way they are clocked: asynchronous and synchronous. Within each of these two categories, counters are classified primarily by the type of sequence, the number of states, or the number of flip-flops in the counter. 1-Asynchronous Counter Operation Asynchronous counters called ripple counters, the first flip-flop is clocked by the external clock pulse and then each successive flip-flop is clocked by the output of the preceding flipflop. The term asynchronous refers to events that do not have a fixed time relationship with each other. An asynchronous counter is one in which the flip-flops within the counter do not change states at exactly the same time because they do not have a common clock pulse. A 2-Bit Asynchronous Binary Counter Fig1-1 shows a 2-bit counter connected for asynchronous operation. Notice that the clock (CLK) is applied to the clock input (C) of only the first flop-flop, FF0, which is always the least significant bit (LSB). The second flip-flop, FF1, is triggered by the Q 0 out-put of FF0. FF0 changes state at the positive-going edge of each clock pulse. But FF1 changes only when triggered by a positive-going transition of the Q 0 output of FF0. Because of the inherent propagation delay tie through a flip-flop, a transition of the input clock pulse (CLK) and a transition of the Q 0 output of FF0 can never occur at exactly the same time. Therefore, the two flip-flops are never simultaneously triggered, so the counter operation is asynchronous. Fig1-1 2-bit asynchronous counter The Timing Diagram Applying 4clock pulses to FF0, Both flip-flops are connected for toggle operation (J=1, K=1) and initially RESET (Q LOW). The positive-going edge of CLK1 (clock pulse1) causes the Q 0 output of FF0 to go HIGH. At the same time the Q 0 output goes LOW, but it has no effect on FF1 because a positive-going transition must occur to trigger the flip-flop. After the leading edge of CLK1, Q 0 =1 & Q 1 =0. The positive-going edge of CLK2 causes Q 0 to go LOW. Q 0 goes HIGH and triggers FF1, causing Q 1 to go HIGH. After the leading edge of CLK2, Q 0 =0 & Q 1 =1. The positive-going edge of CLK3 causes Q 0 to go HIGH again. Output Q 0 goes LOW and has no effect on FF1. Thus, after the leading edge of CLK3, Q 0 =1 & Q 1 =1. The positive-going edge of CLK4 causes Q 0 to go LOW, while Q 0 goes HIGH and triggers 1

2 FF1, causing Q 1 to go LOW. After the leading edge of CLK4, Q 0 =0 & Q 1 =0. The 2-bit counter exhibits four different states, as you would expect with two flip-flops (2 2 = 4). Fig 1-2 Timing diagram for the counter of Fig1-1 Table 1-1Binary state sequence The fourth pulse it recycles to its original state (Q 0 =0, Q 1 =0). The term recycles; it refers to the transition of the counter from its final state back to its original state. A 3-Bit Asynchronous Binary Counter Table1-2 State sequence for a 3-bit binary counter Fig 1-3 Three-bit asynchronous binary counter and its timing diagram for one cycle. 2

3 Fig 1-4Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. Example 1-1: A 4-bit asynchronous binary counter is shown in Fig1-5(a). Each flip-flop is negative edge-triggered and has a propagation delay for 10 ns. Develop a timing diagram showing the Q output of each flip-flop, and determine the total propagation delay time from the triggering edge of a clock pulse until a corresponding change can occur in the state of Q 3, Also determine the maximum clock frequency at which the counter can be operated. Solution: The timing diagram with delays omitted is as shown in Fig1-5(b). For the total delay time, the effect of CLK8 or CLK 16 must propagate through four flip-flops before Q 3 changes, so t P(tot) = 4 x 10 ns = 40 us The maximum clock frequency is f max =1/ t P(tot ) = 1/40 ns = 25 MHz Fig bit asynchronous binary counter and its timing diagram. 3

4 Related Problem: Show the timing diagram if all of the flip-flops in Fig1-5(a) are positive edge- triggered. Asynchronous Decade Counters The modulus is the number of unique states through which the counter will sequence. The maximum possible number of states of a counter is 2 n where n is the number of flip-flops. Counters can be designed to have a number of states in their sequence that is less than the maximum of 2 n. This type of sequence is called a truncated sequence. One common modulus for counters with truncated sequences is 10 (Modules10). A decade counter with a count sequence of zero (0000) through 9 (1001) is a BCD decade counter because its 10-state sequence produces the BCD code. To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible states. A decade counter requires 4 flip-flops. One way to make the counter recycle after the count of 9 (1001) is to decode count 10 (1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR) inputs of the flip-flops, as shown in Fig1-6(a). Partial Decoding: in Fig1-6(a) only Q 1 & Q 3 are connected to the NAND gate inputs. This arrangement is an example of partial decoding, in which the two unique states (Q 1 =1 & Q 3 =1) are sufficient to decode the count of 10 because none of the other states (0 through 9) have both Q 1 & Q 3 HIGH at the same time. Fig 1-6 an asynchronously clocked decade counter with asynchronous recycling. 4

5 Example1-2: Show how an asynchronous counter can be implemented having a modulus of 12 with a straight binary sequence from 0000 through 1011 Solution: 4 flip-flops are required to produce any modulus greater than 8 but less than or equal to 16. When the counter gets to its last state.1011, it must recycle back to 0000 rather than going to its normal next state of 1100, as illustrated in the following sequence chart: Observe that Q 0 & Q 1 both go to 0 anyway, but Q 2 & Q 3 must be forced to 0 on the 12 clock pulse. Fig1-7a shows the modulus-12 counter. The NAND gate partially decodes count 12 (1100) and resets flip-flop2 & flip-flop 3. Thus, on the 12 clock pulse, the counter is forced to recycle from count 11 to count 0, as shown in the timing diagram of fig1-7b. Fig1-7 asynchronously clocked modulus-12 counter with asynchronous recycling Related Problem How can the counter in fig1-7a be modified to make it a modulus-13 counter? 5

6 2- Synchronous counter operation In synchronous counters, the clock input is connected to all of the flip-flops so that they are clocked simultaneously. The term synchronous refers to events that have a fixed time relationship with each other. A 2-Bit Synchronous Binary Counter Fig 1-8 A 2-bit synchronous binary counter First, when the positive edge of the first clock pulse is applied, FF0 will toggle and Q 0 will therefore go HIGH. When FF1at the positive-going edge of CLK1 inputs J 1 & K 1 are both LOW because Q 0 has not yet gone HIGH. So, J 1 =0 & K 1 =0. This is a no-change condition, and therefore FF1 does not change state (fig1-9a). When the leading edge of CLK2 occurs, FF0 will toggle and Q 0 will go LOW and Q 1 goes HIGH. Thus, after CLK2, Q 0 =0 & Q 1 =1 (Fig1-9b). When the leading edge of CLK3 occurs, FF0 again toggles to the SET state (Q 0 = 1), and FF1 remains SET (Q 1 =1. After this triggering edge, Q 0 =1 & Q 1 =1 (Fig1-9c). at the leading edge of CLK4, Q 0 & Q 1 go LOW (Fig1-9d). Fig 1-9 timing details for the1-bit synchronous counter operation Fig 1-10 complete timing diagram for the counter 6

7 A 3-Bit Synchronous Binary Counter Fig bit synchronous counter Fig1-12 the timing diagram A 4-Bit Synchronous Binary Counter Table1-3 Binary state sequence Fig1-13 a 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas. 7

8 A 4-Bit Synchronous Decade Counter Fig1-14 a synchronous BCD decade counters Fig1-15 Timing diagram for the BCD Counter table 1-4 States of a BCD decade 3-Up-Down counter An up/down (bidirectional) counter is one that is capable of progressing in either direction through a certain sequence. An examination of Q 0 for both the up and down sequences shows that FF0 toggles on each clock pulse. Thus, the J 0 & K 0 inputs of FF0 are J 0 =K 0 =1. For the up sequence, Q 1 changes state on the next clock pulse when Q 0 =1. For the down sequence, Q 1 changes on the next clock pulse when Q 0 = 0. Thus, the J 1 & K 1 inputs of FF1 must equal 1 under the conditions expressed by the following equation: J 1 = K 1 = (Q 0.UP) + ( Q 0.DOWN) For the up sequence, Q 2 changes state on the next clock pulse when Q 0 =Q 1 =1. For the down sequence, Q 2 changes on the next clock pulse when Q 0 =Q 1 = 0. Thus, the J 2 & K 2 inputs of FF2 must equal 1 under the conditions expressed by the following equation: J 2 = K 2 = (Q 0.Q 1.UP) + ( Q 0. Q 1.DOWN) Notice that the UP/ DOWN control input is HIGH for UP and LOW for DOWN. 8

9 Fig1-16 a basic 3-bit up/down synchronous counter table1-5 Up/Down sequence Example1-4: Show the timing diagram and determine the sequence of a 4-bit synchronous binary up/down counter if the clock and UP/ DOWN control inputs have waveforms as shown in fig1-7a. The counter starts in the all 0s state and is positive edge-triggered. Solution: From the waveforms of fig2-17b, the counter sequence is as shown in Table 1-6. Fig 1-17 Table 1-6 Related Problem Show the timing diagram if the UP/ DAWN control waveform in fig1-17a is inverted. Design of synchronous counters General Model of a Sequential Circuit a general sequential circuit consists of a combinational logic section and a memory section (flip-flops), as shown in Fig

10 Figure 1-18 General clocked sequential circuit The information stored in the memory section, as well as the inputs to the combinational logic (I 0, I 1,..., I m ), is required for proper operation of the circuit. At any given time the memory is in a state called the present state and will advance to a next state on a clock pulse a determined by conditions on the excitation lines (Y 0, Y 1,..., Y p ) the present state of the memory is represented by the state variables (Q 0, Q 1,..., Q t ). These state variables, along with the inputs (I 0, I 1,,...., I m ) determine the system outputs (O 0, O 1,..., O n ). a general design procedure for sequential circuits is applied to synchronous counters in a series of steps: Step 1: State Diagram The first step in the design of a counter is to create a state diagram. A state diagram shows the progression of states through which the counter advances when it is clocked. As an example, Fig1-19 is a state diagram for a basic 3-bit Gray code counter. This particular circuit has no inputs other than the clock and no outputs other than the outputs taken off each flip-flop in the counter. Fig 1-19 State diagram for a 3-bit Gray code counter Step 2: Next-State Table Once the sequential circuit is defined by a state diagram, the second step is to derive a nextstate table, which lists each state of the counter (present state) along with the corresponding next state. The next state is the state that the counters guess to from its present state upon application of a clock pulse the next-state table is derived from the state diagram and is shown in Table 1-7 for the 3-bit Gray code counter. Q 0 is the least significant bit. 10

11 Table1-7 Next-state table for 3-bit Gray code counter. Step 3: Flip-Flop Transition Table Table 1-8 is a transition table for the J-K flip-flop. All possible output transitions are listed by showing the Q output of the flip-flop going from present states to next states. Q N is the present state of the flip-flop (before a clock pulse) and Q N + 1 is the next state (after a clock pulse). For each output transition the J & K inputs that will cause the transition to occur are listed. An X indicates a "don't care" (the input can be either a 1 or 0). Table1-8 Transition table for a J-K flip-flop To design the counter, the transition table is applied to each of the flip-flops in the counter, based on the next-state table (Table 1-7). For example, for the present state 000, Q 0 goes from a present state of 0 to a next state of 1. To make this happen J 0 must be a 1 and you don't care what K 0 is (J 0 = 1, K 0 = X), as you can see in the transition table (Table 1-8). Next, Q 1 is 0 in the present state and remains 0 in the next state. For this transition, J 1 = 0 & K 1 = X. Q 2 is 0 in the present state and remains 0 in the next state. Therefore, J 2 = 0 & K 2 = X. Step 4: Karnaugh Maps Karnaugh maps can be used to determine the logic required for the J & K inputs of each flipflop in the counter. There is a Karnaugh map for the J input & a Kamaugh map for the K input of each flip-flop. Each cell in a Karnaugh Maps represents one of the present states in the counter sequence listed in Table 1-7. From the J & K states in the transition table (Table 1-8) a 1,0, or X is entered into each present state cell on the maps depending on the transition of the Q output for a particular flip- flop. To illustrate this procedure, two sample entries are shown for the J 0 & K 0 inputs to the least significant flip-flop (Q 0 ) in Fig

12 Fig1-20Examples of the mapping procedure for the counter sequence Fig1-21 Q( ) Karnaugh maps for present-state J & K inputs. 12

13 The completed Karnaugh Maps for all three flip-flops in the counter are shown in fig1-21. The cells are grouped as indicated and the corresponding Boolean expressions for each group are derived. Step 5: logic Expressions for Flip-Flop Inputs From the Karnaugh maps of fig1-21 you obtain the following expressions for the J & K inputs of each flip-flop: Step 6: Counter Implementation The final step is to implement the combinational logic from the expressions for the J & K inputs and connect the flip-flops to form the complete 3-bit Gray code counter as in fig Fig bit Gray code counters A summary of steps used in the design of this counter follows. In general, these steps can be applied to any sequential circuit: 1. Specify the counter sequence and draw a state diagram. 2. Derive a next-state table from the state diagram. 3. Develop a transition table showing the flip-flop inputs required for each transition, The transition table is always the same for a given type of flip-flop. 4. Transfer the J & K states from the transition table to Karnaugh maps. There is a Karnaugh map for each input of each flip-flop. 5. Group the Karnaugh map cells to generate and derive the logic expression for each flipflop input. 6. implement the expressions with combinational logic, and combine with the flip-flops to create the counter. Example1-5:Design a counter with the binary count sequence shown in the state diagram of Fig Use J-K flip-flops. 13

14 Fig1-23 state diagram for Ex5 Solution: Step 1: Although there are only 4 states, a 3-bit counter is required to implement this sequence because the maximum binary count is 7. Since the required sequence dues not include all the possible binary, states, the invalid states (0, 3, 4, & 6) can be treated as "don't cares" in the design. However, if the counter should erroneollsly get into an invalid state, you must make sure that it goes back to a valid state. Step 2: The next-state table is developed from the state diagram and is given in Table 1-9. Table 1-9Next state table Step 3: The transition table for the J-K flip-flop is repeated in Table Table 1-10 transition table for J-K flip-flop Step 4: The J & K inputs are plotted on the present-state Karnaugh maps in fig1-24. Also "don't cares" can be placed in the cells corresponding to the invalid states of 000, 011, 100, and 110, as indicated by the Xs. 14

15 Fig1-24 Step 5: Group the 1s, taking advantage of as many of the "don't care" states as possible for maximum simplification(fig1-24). Notice that when all cells in a map are grouped, the expression is simply equal to1. The expression for each J & K input taken from the maps is as follows: Step 6: The implementation of the counter is shown in Fig1-25. Fig1-25 Analysis shows that if the counter, by accident, gets into one of the invalid states (0, 3, 4, 6 ), it will always return to a valid state according to the following sequences: & 6 1 Cascaded counter Counters can be connected in cascade to achieve higher-modulus operation. In essence, cascading means that the last age output of one counter drives the input of the next counter. An example of two counters connected in cascade is shown in fig1-26 for a 2-bit & a 3-bit ripple counter. Fig1-26 Two cascaded counters (all J & K inputs are HIGH). 15

16 Fig1-27 Timing diagram for the cascaded counter configuration of Fig1-26 The timing diagram is shown in fig1-27. Notice that the final output of the modulus-8 counter, Q 4, occurs once for every 32 input clock pulses. The overall modulus of the cascaded counters is 32; that is, they act as a divide-by-32 counter. When operating synchronous counters in a cascaded configuration, it is necessary to e the count enable and the terminal count functions to achieve higher-modulus operation. On some devices the count enable is CTEN (or G), and terminal count (TC) is analogous to ripple clock output (RCO) on some IC counters. Fig1-28 shows two decade counters connected in cascade. The terminal count (TC) output of counter 1 is connected to the count enable (CTEN) input of counter 2. Counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or terminal, state and its terminal count output goes HIGH. This HIGH now enables counter 2, so that when the first clock pulse after counter 1 reaches its terminal count (CLK10), counter 2 goes from its initial state to its second state. Upon completion of the entire second cycle of counter 1 (when counter 1 reaches terminal count the second time), counter 2 is again enabled and advances to its next state. This sequence continues. Since these are decade counters. Counter1 must go through ten complete cycles be fore counter 2 completes its first cycle. In other words, for every ten cycles of counter 1, counter 2 goes through one cycle. Thus, counter 2 will complete one cycle after one hundred clock pulses. The overall modulus of these two cascaded counters is 10 x 10 = 100. Fig1-28 A modulus-100 counter using two cascaded decade counters. 16

17 When viewed as a frequency divider, the circuit of fig1-28 divides the input clock frequency by 100. Cascaded counters are often used to divide a high-frequency clock signal to obtain highly accurate pulse frequencies. Cascaded counter configurations used for such purposes are sometimes called countdown chains. For example, suppose that you have a basic clock frequency of 1 MHz and you wish to obtain 100 khz, 10 khz, and 1 khz: a series of cascaded decade counters can be used. If the 1 MHz signal is divided by 10, the output is 100 khz. Then if the 100 khz signal is divided by 10, the output is 10 khz. Another division by 10 produces the 1 khz frequency. The general implementation of this countdown in fig1-29 Fig1-29 Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide-by-10 and divide-by-100 outputs. Example1-7 :Determine the overall modulus of the two cascaded counter configurations in fig1-30. Solution: In fig1-30(a), the overall modulus for the 3-counter configuration is: 8 x 12 x 16 = 1536 In fig1-3(b), the overall modulus for the 4-counter configuration is: 10 x 4 x 7 x 5 = 1400 fig 1-30 Related Problem: How many cascaded decade counters are required to divide a clock frequency by 100,000? Counter decoding In many applications, it is necessary that some or all of the counter states be decoded. The decoding of a counter involves using decoders or logic gates to determine when the counter is in a certain binary state in its sequence. Suppose that you wish to decode binary state 6(110) of a 3-bit binary counter. When Q 2 = 1, Q 1 = 1. & Q 0 = 0. a HIGH appears on the output of the decoding gate, indicating that the 17

18 counter is at state 6(fig1-31). This is called active-high decoding. Replacing the AND gate with a NAND gate provides active-low decoding. Fig 1-31 Decoding of state 6 Example:1-9:Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. Show the entire counter timing diagram and the output waveforms of the decoding gates. Binary 2 = Q 2 Q 1 Q 0 and binary 7 = Q 2 Q 1 Q 0. Fig1-32 A 3-bit counter with active HIGH decoding of count 2 and count 7. 18

19 Related Problem Show the logic for decoding state 5 in the 3-bit counter. 1-3 Counter application A Digital Clock :fig1-33 is a simplified logic diagram of a digital clock that displays seconds, minutes, and hours. First, a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform and divided own to a 1Hz pulse waveform by a divide-by-60 counter formed by a divide-by-10 counter allowed by a divide-by-6 counter. Both the seconds and minutes counts are also produced by divide-by-60 counters. These counters count from 0 to 59 and then recycle to 0. Notice that the divide-by-6 is formed with a decade counter with a truncated sequence achieved by using the decoder count 6 to asynchronously clear the counter. The terminal count, 59, is also decoded to enable the next counter in the chain. Fig 1-33 Simplified logic diagram for a 12-hour digital clock The hours counter is implemented with a decade counter and a flip-flop as shown in fig1-34. Consider that initially both the decade counter and the flip-flop are RESET, and the decode- 12 gate and decode-9 gate outputs are HIGH. The decade counter advances through all of its states from zero to nine, and on the clock pulse that recycles it from nine back to zero, the flip-flop goes to the SET state (J=1, K=0). This illuminates a 1 on the tens-of-hours display. The total count is now ten (the decade counter is in the zero state and the flip-flop is SET). Next, the total count advances to eleven and then to twelve. In state 12 the Q2 output of the decade counter is HIGH, the flip-flop is still SET, and thus the decode-12 gate output is LOW. This activates the PE input of the decade counter. On the next clock pulse, the decade Counter is preset to state I by the data inputs, and the flip-flop is RESET (J=0, K=1). As you can see, this logic always causes the counter to recycle from twelve back to one rather than back to zero. 19

20 Fig 1-34 Logic diagram of typical divide-by-60 counter using synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB). Fig1-35 Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LS B. 20

21 Digital logic with feedback the nature of an OR gate: any high (1) input forces the output high (1). If A is low (0), however, we cannot guarantee the logic level or state of the output in our truth table. Since the output feeds back to one of the OR gate s inputs, and we know that any 1 input to an OR gates makes the output 1, this circuit will latch in the 1 output state after any time that A is 1. When A is 0, the output could be either 0 or 1, depending on the circuit s prior state! The proper way to complete the above truth table would be to insert the word latch in place of the question mark, showing that the output maintains its last state when A is 0. Any digital circuit employing feedback is called a multivibrator. The example we just explored with the OR gate was a very simple example of what is called a bistable multivibrator. It is called bistable because it can hold stable in one of two possible output states, either 0 or 1. There are also monostable multivibrators, which have only one stable output state (that other state being momentary), and astable multivibrators, which have no stable state (oscillating back and forth between an output of 0 and 1). A very simple astable multivibrator is an inverter with the output fed directly back to the input: When the input is 0, the output switches to 1. That 1 output gets fed back to the input as a 1. When the input is 1, the output switches to 0. That 0 output gets fed back to the input as a 0, and the cycle repeats itself. The result is a high frequency (several megahertz) oscillator The S-R latch 1

22 Any circuit with two or more vibrators linked together is a multivibrator, a bistable multivibrator has two stable states, as indicated by the prefix bi in its name. Typically, one state is referred to as set and the other as reset. The simplest bistable device, therefore,is known as a set-reset, or S-R, latch. To create an S-R latch, we can wire two NOR gates in such a way that the output of one feeds back to the input of another, and vice versa, like this: The Q & Q outputs are supposed to be in opposite states. I say supposed to because making both the S and R inputs equal to 1 results in both Q & Q being 0. For this reason, having both S and R equal to 1 is called an invalid or illegal state for the S-R multivibrator. Otherwise, making S=1 and R=0 (sets) the multivibrator so that Q=1 & Q=0. Conversely, making R=1 and S=0 (resets) the multivibrator in the opposite state. When S and R are both equal to 0, the multivibrator s outputs (latch) in their prior states. By definition, a condition of Q=1 & Q=0 is set. A condition of Q=0& Q =1 is reset. These terms are universal in describing the output states of any multivibrator circuit. Note that the initial power-up condition of either the gate of S-R latch is such that both gates (coils) start in the de-energized mode. As such, one would expect that the circuit will start up in an invalid condition, with both Q & Q outputs being in the same state. Actually, this is true! However, the invalid condition is unstable with both S and R inputs inactive, and the circuit will quickly stabilize in either the set or reset condition because one gate is bound to react a little faster than the other. Race conditions should be avoided in circuit design primarily for the unpredictability that will be created. One way to avoid such a condition is to insert a time-delay relay into the circuit to disable one of the competing relays for a short time, giving the other one a clear advantage. In other words, by purposely slowing down the de-energization of one relay, we ensure that the other relay will always win and the race results will always be predictable. Review: 1- A bistable multivibrator is one with two stable output states. 2-In a bistable multivibrator, the condition of Q=1 & Q =0 is defined as set. A condition of Q=0 & Q =1 is conversely defined as reset. If Q & Q happen to be forced to the same state (both 0 or both 1), that state is referred to as invalid. 3-In an S-R latch, activation of the S input sets the circuit, while activation of the R input resets the circuit. If both S and R inputs are activated simultaneously, the circuit will be in an invalid condition. 4-A race condition is a state in a sequential system where two mutually-exclusive events are simultaneously initiated by a single cause. The gated S-R latch 2

23 It is sometimes useful in logic circuits to have a multivibrator which changes state only when certain conditions are met, regardless of its S and R input states. The conditional input is called the enable, and is symbolized by the letter E. Study the following example to see how this works: When the E=0, the outputs of the two AND gates are forced to 0, regardless of the states of either S or R. Consequently, the circuit behaves as though S and R were both 0, latching the Q & Q outputs in their last states. Only when the enable input is activated (1) will the latch respond to the S and R inputs. Note the identical function in ladder logic: A practical application of this might be the same motor control circuit (with two normallyopen pushbutton switches for start and stop), except with the addition of a master lockout input (E) that disables both pushbuttons from having control over the motor when it s low (0). REVIEW: 1-The enable input on a multivibrator must be activated for either S or R inputs to have any effect on the output state. 2-This enable input is sometimes labeled E, and other times as EN. The D latch Since the enable input on a gated S-R latch provides a way to latch the Q & Q outputs without regard to the status of S or R, we can eliminate one of those inputs to create a multivibrator latch circuit with no illegal input states. Such a circuit is called a D latch, and its internal logic looks like this: Note that the R input has been replaced with the complement (inversion) of the old S input, and the S input has been renamed to D. As with the gated S-R latch, the D latch will not respond to a signal input if the enable input is 0 it simply stays latched in its last state. When the enable input is 1, however, the Q output follows the D input. Since the R input of the S-R circuitry has been done away with, this latch has no invalid or illegal state. Q & Q are always opposite of one another. 3

24 Like both the S-R and gated S-R latches, the D latch circuit may be found as its own prepackaged circuit, complete with a standard symbol: The D latch is nothing more than a gated S-R latch with an inverter added to make R the complement (inverse) of S. Let s explore the ladder logic equivalent of a D latch, modified from the basic ladder diagram of an S-R latch: An application for the D latch is a 1-bit memory circuit. You can write (store) a 0 or 1 bit in this latch circuit by making the enable input high (1) and setting D to whatever you want the stored bit to be. When the enable input is made low (0), the latch ignores the status of the D input and merrily holds the stored bit value, outputting at the stored value at Q, and its inverse on output Q. REVIEW: 1-A D latch is like an S-R latch with only one input: the D input. Activating the D input sets the circuit, and de-activating the D input resets the circuit. Of course, this is only if the enable input (E) is activated as well. Otherwise, the output(s) will be latched, unresponsive to the state of the D input. 2-D latches can be used as 1-bit memory circuits, storing either a high or a low state when disabled, and reading new data from the D input when enabled. Edge-triggered latches: Flip-Flops The latch responds to the data inputs (S-R or D) only when the enable input is activated. In many digital applications, it is desirable to limit the responsiveness of a latch circuit to a very short period of time instead of the entire duration that the enabling input is activated. One method of enabling a multivibrator circuit is called edge triggering, where the circuit s data inputs have control only during the time that the enable input is transitioning from one state to another.let s compare timing diagrams for a normal D latch versus one that is edge-triggered: In the first timing diagram, the outputs respond to input D whenever the enable (E) input is high, for however long it remains high. When the enable signal falls back to a low state, the circuit remains latched. In the second timing diagram, we note a distinctly different response in the circuit output(s): it only responds to the D input during that brief moment of time when the enable signal changes, or transitions, from low to high. This is known as positive edge triggering. There is such a thing as negative edge triggering as well, and it produces the following response to the same input signals: 4

25 Whenever we enable a multivibrator circuit on the transitional edge of a square-wave enable signal, we call it a flip-flop instead of a latch. Consequently, and edge-triggered S-R circuit is more properly known as an S-R flip-flop, and an edge-triggered D circuit as a D flip-flop. The enable signal is renamed to be the clock signal. Also, we refer to the data inputs (S, R, and D, respectively) of these flip-flops as synchronous inputs, because they have effect only at the time of the clock pulse edge (transition), thereby synchronizing any output changes with that clock pulse, rather than at the data inputs. But, how do we actually accomplish this edge-triggering? What we need is a digital circuit that outputs a brief pulse whenever the input is activated for an arbitrary period of time, and we can use the output of this circuit to briefly enable the latch. We re getting a little ahead of ourselves here, but this is actually a kind of monostable multivibrator, which for now we ll call a pulse detector. The duration of each output pulse is set by components in the pulse circuit itself. In ladder logic, this can be accomplished quite easily through the use of a time-delay relay with a very short delay time: Implementing this timing function with semiconductor components is actually quite easy, as it exploits the inherent time delay within every logic gate (known as propagation delay). What we do is take an input signal and split it up two ways, then place a gate or a series of gates in one of those signal paths just to delay it a bit, then have both the original signal and its delayed counterpart enter into a two-input gate that outputs a high signal for the brief moment of time that the delayed signal has not yet caught up to the low-to-high change in the non-delayed signal. An example circuit for producing a clock pulse on a low-to-high input signal transition is shown here: 5

26 This circuit may be converted into a negative-edge pulse detector circuit with only a change of the final gate from AND to NOR: Now that we know how a pulse detector can be made, we can show it attached to the enable input of a latch to turn it into a flip-flop. In this case, the circuit is a S-R flip-flop: Only when the clock signal (C) is transitioning from low to high is the circuit responsive to the S and R inputs. For any other condition of the clock signal ( x ) the circuit will be latched. A ladder logic version of the S-R flip-flop is shown here: It is important to note that the invalid state for the S-R flip-flop is maintained only for the short period of time that the pulse detector circuit allows the latch to be enabled. After that brief time period has elapsed, the outputs will latch into either the set or the reset state. Once again, the problem of a race condition manifests itself. With no enable signal, an invalid output state cannot be maintained. However, the valid latched states of the multivibrator set and reset are mutually exclusive to one another. Therefore, the two gates of the multivibrator circuit will race each other for supremacy, and whichever one attains a high output state first will win. The block symbols for flip-flops are slightly different from that of their respective latch counterparts: The positive edge-triggered- Negative edge-triggered with a bubble on the clock input The triangle symbol next to the clock inputs tells us that these are edge-triggered devices, and consequently that these are flip-flops rather than latches. 6

27 Both of the above flip-flops will clock on the falling edge (high-to-low transition) of the clock signal. Review: 1-A flip-flop is a latch circuit with a pulse detector circuit connected to the enable (E) input, so that it is enabled only for a brief moment on either the rising or falling edge of a clock pulse. 2-Pulse detector circuits may be made from time-delay relays for ladder logic applications, or from semiconductor gates (exploiting the phenomenon of propagation delay). The J-K flip-flop Another variation on a theme of bistable multivibrators is the J-K flip-flop. Essentially, this is a modified version of an S-R flip-flop with no invalid or illegal output state. Look closely at the following diagram to see how this is accomplished What used to be the S and R inputs are now called the J and K inputs, respectively. The old twoinput AND gates have been replaced with 3-input AND gates, and the third input of each gate receives feedback from the Q & Q outputs. What this does for us is permit the J input to have effect only when the circuit is reset, and permit the K input to have effect only when the circuit is set. In other words, the two inputs are interlocked, to use a relay logic term, so that they cannot both be activated simultaneously. If the circuit is set, the J input is inhibited by the 0 status of Q through the lower AND gate; if the circuit is reset, the K input is inhibited by the 0 status of Q through the upper AND gate. When both J and K inputs are 1, however, something unique happens. Because of the selective inhibiting action of those 3-input AND gates, a set state inhibits input J so that the flip-flop acts as if J=0 while K=1 when in fact both are 1. On the next clock pulse, the outputs will switch ( toggle ) from set (Q=1 & Q=0) to reset (Q=0 & Q=1). Conversely, a reset state inhibits input K so that the flip-flop acts as if J=1 and K=0 when in fact both are 1. The next clock pulse toggles the circuit again from reset to set. The end result is that the S-R flip-flop s invalid state is eliminated (along with the race condition it engendered) and we get a useful feature as a bonus: the ability to toggle between the two (bistable) output states with every transition of the clock input signal. There is no such thing as a J-K latch, only J-K flip-flops. Without the edge-triggering of The end result is that the S-R flip-flop s invalid state is eliminated (along with the race condition it engendered) and we get a useful feature as a bonus: the ability to toggle between the two (bistable) output states with every transition of the clock input signal. There is no such thing as a J-K latch, only J-K flip-flops. Without the edge-triggering of The end result is that the S-R flip-flop s invalid state is eliminated (along with the race condition 7

28 it engendered) and we get a useful feature as a bonus: the ability to toggle between the two (bistable) output states with every transition of the clock input signal. the clock input, the circuit would continuously toggle between its two output states when both J and K were held high (1), making it an astable device instead of a bistable device in that circumstance. If we want to preserve bistable operation for all combinations of input states, we must use edge-triggering so that it toggles only when we tell it to, one step (clock pulse) at a time.the block symbol for a J-K flip-flop is a whole lot less frightening than its internal circuitry, and just like the S-R and D flip-flops, J-K flip-flops come in two clock varieties (negative and positive edge-triggered): REVIEW: 1- A J-K flip-flop is nothing more than an S-R flip-flop with an added layer of feedback. This feedback selectively enables one of the two set/reset inputs so that they cannot both carry an active signal to the multivibrator circuit, thus eliminating the invalid condition. 2-When both J and K inputs are activated, and the clock input is pulsed, the outputs (Q & Q ) will swap states. That is, the circuit will toggle from a set state to a reset state, or vice versa. Asynchronous flip-flop inputs The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous nputs because they have effect on the outputs (Q & Q ) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they re called preset and clear: When the preset input is activated, the flip-flop will be set (Q=1, Q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, & Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q & Q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once. Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they re active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs Sometimes the designations PRE and CLR will be shown with inversion bars above them, to further denote the negative logic of these inputs: Review: 8

29 1-Asynchronous inputs on a flip-flop have control over the outputs (Q & Q) regardless of clock input status. 2-These inputs are called the preset (PRE) and clear (CLR). The preset input drives the flip-flop to a set state while the clear input drives it to a reset state. 3-It is possible to drive the outputs of a J-K flip-flop to an invalid condition using the asynchronous inputs, because all feedback within the multivibrator circuit is overridden. Monostable multivibrators We ve already seen one example of a monostable multivibrator in use: the pulse detector used within the circuitry of flip-flops, to enable the latch portion for a brief time when the clock input signal transitions from either low to high or high to low. The pulse detector is classified as a monostable multivibrator because it has only one stable state. By stable, I mean a state of output where the device is able to latch or hold to forever, without external prodding. A latch or flip-flop, being a bistable device, can hold in either the set or reset state for an indefinite period of time. Once its set or reset, it will continue to latch in that state unless prompted to change by an external input. A monostable device, on the other hand, is only able to hold in one particular state indefinitely. Its other state can only be held momentarily when triggered by an external input. A mechanical analogy of a monostable device would be a momentary contact pushbutton switch, which spring-returns to its normal (stable) position when pressure is removed from its button actuator. Likewise, a standard wall (toggle) switch, such as the type used to turn lights on and off in a house, is a bistable device. It can latch in one of two modes: on or off. All monostable multivibrators are timed devices. That is, their unstable output state will hold only for a certain minimum amount of time before returning to its stable state. With semiconductor monostable circuits, this timing function is typically accomplished through the use of resistors and capacitors, making use of the exponential charging rates of RC circuits. A comparator is often used to compare the voltage across the charging (or discharging) capacitor with a steady reference voltage, and the on/off output of the comparator used for a logic signal. With ladder logic, time delays are accomplished with time-delay relays, which can be constructed with semiconductor/rc circuits like that just mentioned, or mechanical delay devices which impede the immediate motion of the relay s armature. Note the design and operation of the pulse detector circuit in ladder logic: No matter how long the input signal stays high (1), the output remains high for just 1 second of time, then returns to its normal (stable) low state. For some applications, it is necessary to have 9

30 a monostable device that outputs a longer pulse than the input pulse which triggers it. Consider the following ladder logic circuit: When the input contact closes, TD1 contact immediately closes, and stays closed for 10 seconds after the input contact opens. No matter how short the input pulse is, the output stays high (1) for exactly 10 seconds after the input drops low again. This kind of monostable multivibrator is called a one-shot. More specifically, it is a retriggerable one-shot, because the timing begins after the input drops to a low state, meaning that multiple input pulses within 10 seconds of each other will maintain a continuous high output: One application for a retriggerable one-shot is that of a single mechanical contact debouncer. As you can see from the above timing diagram, the output will remain high despite bouncing of the input signal from a mechanical switch. Of course, in a real-life switch debouncer circuit, you d probably want to use a time delay of much shorter duration than 10 seconds, as you only need to debounce pulses that are in the millisecond range. What if we only wanted a 10 second timed pulse output from a relay logic circuit, regardless of how many input pulses we received or how long-lived they may be? In that case, we d have to couple a pulse-detector circuit to the retriggerable one-shot time delay circuit, like this: Time delay relay TD1 provides an on pulse to time delay relay coil TD2 for an arbitrarily short moment (in this circuit, for at least 0.5 second each time the input contact is actuated). As soon as TD2 is energized, the normally-closed, timed-closed TD2 contact in series with it prevents coil TD2 frombeing re-energized as long as its timing out (10 seconds). This effectively makes it unresponsive to any more actuations of the input switch during that 10 second period. Only after TD2 times out does the normally-closed, timed-closed TD2 contact in series with it allow coil TD2 to be energized again. This type of one-shot is called a nonretriggerable oneshot. 10

31 One-shot multivibrators of both the retriggerable and nonretriggerable variety find wide application in industry for siren actuation and machine sequencing, where an intermittent input signal produces an output signal of a set time. Review: 1-A monostable multivibrator has only one stable output state. The other output state can only be maintained temporarily. 2-Monostable multivibrators, sometimes called one-shots, come in two basic varieties: retriggerable and nonretriggerable. 3-One-shot circuits with very short time settings may be used to debounce the dirty signals created by mechanical switch contacts. 11

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