WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "WEEK 8.1 Registers and Counters. ECE124 Digital Circuits and Systems Page 1"

Transcription

1 WEEK 8.1 egisters and Counters ECE124 igital Circuits and Systems Page 1

2 Additional schematic FF symbols Active low set and reset signals. S Active high set and reset signals. S ECE124 igital Circuits and Systems Page 2

3 Characteristic tables and equations for FFs We can describe the behavior of a flip-flop via a characteristic table. The characteristic table shows what the next flip-flop output value will be given the current flip-flop input value after the clock makes its active edge transition. We can also write this as a characteristic equation: ECE124 igital Circuits and Systems Page 3

4 Toggle flip-flops (TFF) Another type of flip-flop that has a different behavior when compared to a FF. Symbol for a positive edge-triggered TFF: T Symbol for a negative edge-triggered TFF: T ECE124 igital Circuits and Systems Page 4

5 Characteristic tables and equations for TFFs The characteristic table for the TFF: The characteristic equation for the TFF: So with a TFF, the output toggles (or flips) its value if the input is T=1, otherwise it remains the same. ECE124 igital Circuits and Systems Page 5

6 Making a TFF from a FF We can actually build a TFF using a FF and a 2-input XO gate. T T CLOCK ECE124 igital Circuits and Systems Page 6

7 JK flip-flops (JKFF) Another type of flip-flop that has different behavior compared to a FF or to a TFF. Positive edge-triggered JKFF: J K Negative edge-triggered JKFF: ECE124 igital Circuits and Systems Page 7

8 Characteristic tables and equations for JKFFs The characteristic table for the JKFF: We can derive the characteristic equation for the JKFF (I find it easy to explain via a K- Map): JK (t) ECE124 igital Circuits and Systems Page 8

9 Making a JKFF from a FF We can actually build a JKFF using a FF and some other gates. J J K CLOCK K ECE124 igital Circuits and Systems Page 9

10 Timing analysis with flip-flops There are some important things to understand when we go to actually make and implement a circuit with flip-flops. In reality, it takes time for gates to change their output values according to the input values i.e., there are propagation delays due to resistance, capacitance, etc. Changes in flip-flop outputs occur at the active clock edge. There are three timing parameters that are especially important: Setup Time (TSU). Hold Time (TH). Clock-To-Output Time (TCO). ECE124 igital Circuits and Systems Page 10

11 efinitions for timing analysis of flip-flops Setup Time (TSU): The setup time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) PIO to the arrival of the active clock edge. Hold Time (TH): The hold time of a flip-flop is the amount of time that the data inputs need to be held stable (not changing) AFTE the arrival of the active clock edge. Clock-To-Output (TCO): The clock-to-output time of a flip-flop is the amount of time it takes for the output to become stable (at its new value) AFTE the arrival of the active clock edge. ECE124 igital Circuits and Systems Page 11

12 Comments If these timing specifications are not met, then it is possible that the flip-flop will not behave as expected. That is, if we don t observe setup and hold times at the data inputs, then our output might not change as expected. That is, if we don t wait long enough (clock-to-output time) for the output to change, then we might use an incorrect value. If we violate any of these timing parameters, then we have a timing violation. These timing parameters (as we will see later) have an influence on how fast we can clock a circuit. ECE124 igital Circuits and Systems Page 12

13 Illustration of timing parameters (for a FF) TSU TH TCO CLOCK should not change in this interval not stable (trustworthy) until this interval ends ECE124 igital Circuits and Systems Page 13

14 egisters A single FF stores one bit A group of n FFs stores n-bits and is called an n-bit register. I0 A0 Illustration: When clear=0, all flip-flop outputs are forced to zero (active low reset). I1 A1 When clear=1, the rising edge of the clock (the active clock edge), results in the 4-bit input transferred to register output. I2 A2 I3 A3 clock clear ECE124 igital Circuits and Systems Page 14

15 Parallel loads (1) We might want to prevent the transfer of data from input to output even though the active clock edge arrives we want the register to HOL ITS CUENT VALUE. We can do this by feeding the register outputs back to the inputs and adding some additional logic to control the register operation. ECE124 igital Circuits and Systems Page 15

16 Parallel loads (2) When load=1, the data inputs reach the -input of the flip-flop. When the active clock edge arrives, the data gets transferred, or loaded, to the register output. When load=0, the data output of each flip-flop is fed back to its -input. I0 I1 A0 A1 When the active clock edge arrives, the data input gets transferred to the register output, but since the values are the same for all flip-flops, the register holds its current value. I2 I3 A2 A3 load clock clear ECE124 igital Circuits and Systems Page 16

17 Shift registers Might want a register that can shift data serially in a direction This type of register is called a shift register. Illustration of a 4-bit shift register. serial in serial out clock clear As active clock edges arrive, the data present at the serial input gets transferred towards the serial output so, data gets shifted to the right one bit at a time as clock edges arrive. ECE124 igital Circuits and Systems Page 17

18 Comment Whenever we would like to add an operation to our register, we are simply placing a MUX in from of each FF in order to direct the correct information to the FF inputs in order to obtain the correct operation. ECE124 igital Circuits and Systems Page 18

19 Universal shift registers (1) Perhaps we want a more general circuit e.g., we want to be able to clear the register, load the register, and perform both a shift right and a shift left operation. ECE124 igital Circuits and Systems Page 19

20 Universal shift registers (2) 4-bit register capable of multiple operations (use multiplexers instead of AN/O gates at FF inputs): data in (rshift) I A0 I A1 I A2 I A3 data in (lshift) c1 c0 clock clear ECE124 igital Circuits and Systems Page 20

21 Universal shift registers (3) Has an asynchronous clear signal Has a clock signal Has data inputs for parallel load Has data inputs for both left and right shifts Has two control inputs that determine behavior: ECE124 igital Circuits and Systems Page 21

22 Counters A counter is a register whose outputs go through a prescribed sequence of states upon the arrival of the active edge of some triggering signal (e.g., like a clock). The prescribed sequence of states, or register outputs, can be anything. Counters can come in two varieties asynchronous or synchronous. ECE124 igital Circuits and Systems Page 22

23 ipple counters ipple counters consist of a series of flip-flops where the output of one flip-flop is used (somehow) as the clock for the next flip-flop. It is the lack of a common clock signal for each flip-flop that makes the counter asynchronous. ECE124 igital Circuits and Systems Page 23

24 Binary ripple counter (1) A type of ripple counter that has n-bits, and can count in binary from 0 to 2 n -1 and repeat. E.g., count sequence for 4-bits: ECE124 igital Circuits and Systems Page 24

25 Binary ripple counter (2) We can make a binary ripple counter easily via observation 1 count T A0 A 0 always flips A 1 flips with A 0 goes 1 -> 0 T A1 A 2 flips with A 1 goes 1 -> 0 Etc So, the i-th bit complements the (i+1)-th bit when it goes 1 -> 0. T A2 Binary ripple counter easily done with TFFs. T A3 clear ECE124 igital Circuits and Systems Page 25

26 Up and down binary ripple counters Up counters count in the sequence 0, 1, 2,, 2 n -1 and repeats. own counters count in the sequence 2 n -1,, 2, 1, 0 and repeats. Should be able to take our previous example and construct a binary ripple down counter ECE124 igital Circuits and Systems Page 26

27 ipple counter delays ecall: Flip-flops have clock-to-output times (it takes time for the output to change once the clock signal arrives on the flip-flop). Because of this, it can take a lot of time for the higher order bits of a ripple counter to change (remember that the i-th bit output is used as the clock for the (i+1)-th bit). count A0 A1 A2 A3 transition time due to clock-to-output times So, the FF outputs do not change at the same time due to the ripple effect in the clock inputs. We would like FF outputs to change simultaneously. This is why we prefer to design synchronous counters. ECE124 igital Circuits and Systems Page 27

28 Synchronous counters ifferent from ripple counters in that (the same) clock pulses are applied to the clock inputs of all flip-flops simultaneously. Flip-flop outputs then change simultaneously. ECE124 igital Circuits and Systems Page 28

29 Example: Synchronous Binary Up Counter Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count. Observation: A 0 is always toggling, A 1 toggles if A 0 is 1, A 2 toggles if A 0, A 1 are 1, A 3 toggles if A 0, A 1, A 2 are 1 Observations motivate the use of TFF ECE124 igital Circuits and Systems Page 29

30 Example: Synchronous Binary Up Counter Synchronous 4-bit binary up counter with enable using TFF: enable T A0 T A1 T A2 T A3 clock clear next stage ECE124 igital Circuits and Systems Page 30

31 Example: Synchronous Binary own Counter Can design a 4-bit synchronous binary up counter with enable: If enable=0 circuit should not count; If enable=1 the circuit should count. Observation: A 0 is always toggling, A 1 toggles if A 0 is 0 A 2 toggles if A 0, A 1 are 0, A 3 toggles if A 0, A 1, A 2 are 0 Observations motivate the use of TFF ECE124 igital Circuits and Systems Page 31

32 Example: Synchronous Binary own Counter Synchronous 4-bit binary down counter with enable using TFF: down T A0 T A1 T A2 T A3 clock clear next stage ECE124 igital Circuits and Systems Page 32

33 Example: Synchronous Binary Up/own Counter Can combine the up and down counter to get an up/down counter (re-use previously built circuits!) Trick is getting correct input to the FF in order to perform correct operation. Consider the following control inputs which determine circuit behaviour: ECE124 igital Circuits and Systems Page 33

34 Example: Synchronous Binary Up/own Counter Have both logic for up count and down count; up has priority (it disables down). ECE124 igital Circuits and Systems Page 34

35 Example: Synchronous Binary Up/own Counter With Parallel Load Often useful to have a counter that we can load with a starting count. This requires adding another control line (load) and data inputs: ECE124 igital Circuits and Systems Page 35

36 Example: Synchronous Binary Up/own Counter With Parallel Load load up down L U I0 T A0 I1 T A1 I2 T A2 I3 T A3 clock clear ECE124 igital Circuits and Systems Page 36

37 Comments All of the previous counters could have been built using FF or JKFF. esigning counters that perform multiple operations involves: Making sure that the correct inputs get to the FF inputs in order to perform the specific function; and The logic feeding the FF input will cause the FF output to change appropriately. If the control signals and operations have priority, we need to make sure that the control signal priority disables the operation due to other control lines (e.g., parallel load turns off up/down count signals. ECE124 igital Circuits and Systems Page 37

38 Symbols We might have different symbols to represent counters: E.g., I0 I1 I2 I3 CL UP A0 A1 A2 A3 ECE124 igital Circuits and Systems Page 38

39 Modulo counters Sometimes we don t want to count through the entire sequence of binary numbers. E.g., we might want to count 0, 1,,2,, 10 and repeat. (This is effectively a modulo- 10 counter). We could design such a counter using synchronous circuit design principles, but we could also attempt something a bit trickier We can use additional circuitry to detect our maximum count number and use a parallel load to restart the counting. ECE124 igital Circuits and Systems Page 39

40 Modulo counter build from a binary counter building block E.g., design a counter that counts 0, 1,,2,, 10 and repeats. CLK I0 A0 I1 A1 I2 A2 I3 A3 CL UP LOA ECE124 igital Circuits and Systems Page 40

41 Some Other Types of Counters: ing counters An n-bit counter in which only one output is high at any given time. E.g., Can illustrate with a timing diagram for 4-bits: CLK A0 A1 A2 A3 Outputs like this useful to generate timing signals that indicate an order of operation in another circuit block. ECE124 igital Circuits and Systems Page 41

42 Some Other Types of Counters: ing counters Can make an n-bit ring counter with a shift register. E.g., 4-bit ring counter: A0 A1 A2 A3 S clear clk To generate n non-overlapping timing signals, we need a shift register with n flip-flops. ECE124 igital Circuits and Systems Page 42

43 Some Other Types of Counters: ing counters Can also use a combination of a counter and a decoder. E.g., 4-bit ring counter with 2-bit counter and decoder. 1 CL A0 A1 x y 0 1 A0 A1 CLK 1 COUNT 2 3 A2 A3 2-bit counter 2-to-4 decoder ECE124 igital Circuits and Systems Page 43

44 Some Other Types of Counters: Switch-tail ring counters Consider the following 4-bit circuit: A0 A1 A2 A3 clear clk esembles a 4-bit ring counter, but complement of MSB fed back to LSB. ECE124 igital Circuits and Systems Page 44

45 Some Other Types of Counters: Switch-tail ring counters Count pattern can be determined: So, with n bits we get a count pattern of 2 n output states. ECE124 igital Circuits and Systems Page 45

46 Some Other Types of Counters: Johnson counters We can add additional detection circuitry in order to generate the disjoint timing signals like a ring counter. This results in a Johnson Counter. With a Johnson Counter, we can get 2 n non-overlapping timing signals using n flip-flops and some extra 2-input AN gates. ECE124 igital Circuits and Systems Page 46

47 Closing emarks Synchronous counters are nice because the counter outputs all change at the same time (according to the clock). We have only talked about some types of counters; e.g., Binary up/down counters; modulo counters. In general, counters are simply an example of a clocked sequential circuit. We can design any type of counter (e.g., any sequence of values we want) once we learn about clocked sequential circuit design (coming up in the course). E.g., we will see how to design a counter that counts 0, 3, 5, 4, 1, and repeats (if we wanted to). ECE124 igital Circuits and Systems Page 47

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation

More information

Module 3: Floyd, Digital Fundamental

Module 3: Floyd, Digital Fundamental Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : yongsheng.gao@griffith.edu.au Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental

More information

Counters & Shift Registers Chapter 8 of R.P Jain

Counters & Shift Registers Chapter 8 of R.P Jain Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without

More information

Digital Logic Design Sequential circuits

Digital Logic Design Sequential circuits Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: ahmed.madian@guc.edu.eg Dr. Eng. Rania.Swief E-mail: rania.swief@guc.edu.eg Dr. Eng. Ahmed H. Madian Registers An n-bit register

More information

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse.

DIGITAL COUNTERS. Q B Q A = 00 initially. Q B Q A = 01 after the first clock pulse. DIGITAL COUNTERS http://www.tutorialspoint.com/computer_logical_organization/digital_counters.htm Copyright tutorialspoint.com Counter is a sequential circuit. A digital circuit which is used for a counting

More information

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.

To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital

More information

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters:

Design Example: Counters. Design Example: Counters. 3-Bit Binary Counter. 3-Bit Binary Counter. Other useful counters: Design Eample: ers er: a sequential circuit that repeats a specified sequence of output upon clock pulses. A,B,C,, Z. G, O, T, E, R, P, S,!.,,,,,,,7. 7,,,,,,,.,,,,,,,,,,,. Binary counter: follows the binary

More information

Counters and Decoders

Counters and Decoders Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter

More information

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies

ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation

More information

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann

Chapter 7. Registers & Register Transfers. J.J. Shann. J. J. Shann Chapter 7 Registers & Register Transfers J. J. Shann J.J. Shann Chapter Overview 7- Registers and Load Enable 7-2 Register Transfers 7-3 Register Transfer Operations 7-4 A Note for VHDL and Verilog Users

More information

Chapter 8. Sequential Circuits for Registers and Counters

Chapter 8. Sequential Circuits for Registers and Counters Chapter 8 Sequential Circuits for Registers and Counters Lesson 3 COUNTERS Ch16L3- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline Counters T-FF Basic Counting element State

More information

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS

CHAPTER IX REGISTER BLOCKS COUNTERS, SHIFT, AND ROTATE REGISTERS CHAPTER IX-1 CHAPTER IX CHAPTER IX COUNTERS, SHIFT, AN ROTATE REGISTERS REA PAGES 249-275 FROM MANO AN KIME CHAPTER IX-2 INTROUCTION -INTROUCTION Like combinational building blocks, we can also develop

More information

Counters are sequential circuits which "count" through a specific state sequence.

Counters are sequential circuits which count through a specific state sequence. Counters Counters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage:

More information

Asynchronous counters, except for the first block, work independently from a system clock.

Asynchronous counters, except for the first block, work independently from a system clock. Counters Some digital circuits are designed for the purpose of counting and this is when counters become useful. Counters are made with flip-flops, they can be asynchronous or synchronous and they can

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 igital Logic Flip-Flops, Registers and Counters: Flip-Flops r.. J. Jackson Lecture 25- Flip-flops The gated latch circuits presented are level sensitive and can change states more than once during

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute. 2nd (Spring) term 2012/2013 DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 4. LECTURE: COUNTERS AND RELATED 2nd (Spring) term 2012/2013 1 4. LECTURE: COUNTERS AND RELATED 1. Counters,

More information

Contents COUNTER. Unit III- Counters

Contents COUNTER. Unit III- Counters COUNTER Contents COUNTER...1 Frequency Division...2 Divide-by-2 Counter... 3 Toggle Flip-Flop...3 Frequency Division using Toggle Flip-flops...5 Truth Table for a 3-bit Asynchronous Up Counter...6 Modulo

More information

Lesson 12 Sequential Circuits: Flip-Flops

Lesson 12 Sequential Circuits: Flip-Flops Lesson 12 Sequential Circuits: Flip-Flops 1. Overview of a Synchronous Sequential Circuit We saw from last lesson that the level sensitive latches could cause instability in a sequential system. This instability

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: omputer Organization and Architecture Lecture 8: Registers and ounters Registers A register is a group of flip-flops. Each flip-flop stores one bit of data; n flip-flops are required to store

More information

Memory Elements. Combinational logic cannot remember

Memory Elements. Combinational logic cannot remember Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic

More information

CHAPTER 11 LATCHES AND FLIP-FLOPS

CHAPTER 11 LATCHES AND FLIP-FLOPS CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

More information

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng

Digital Logic Design. Basics Combinational Circuits Sequential Circuits. Pu-Jen Cheng Digital Logic Design Basics Combinational Circuits Sequential Circuits Pu-Jen Cheng Adapted from the slides prepared by S. Dandamudi for the book, Fundamentals of Computer Organization and Design. Introduction

More information

Digital Fundamentals

Digital Fundamentals Digital Fundamentals Tenth Edition Floyd hapter 8 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved ounting in Binary As you know, the binary count sequence

More information

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012

Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR

More information

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department

DIGITAL ELECTRONICS. Counters. By: Electrical Engineering Department Counters By: Electrical Engineering Department 1 Counters Upon completion of the chapter, students should be able to:.1 Understand the basic concepts of asynchronous counter and synchronous counters, and

More information

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012

Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012 Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

BINARY CODED DECIMAL: B.C.D.

BINARY CODED DECIMAL: B.C.D. BINARY CODED DECIMAL: B.C.D. ANOTHER METHOD TO REPRESENT DECIMAL NUMBERS USEFUL BECAUSE MANY DIGITAL DEVICES PROCESS + DISPLAY NUMBERS IN TENS IN BCD EACH NUMBER IS DEFINED BY A BINARY CODE OF 4 BITS.

More information

Asynchronous Counters. Asynchronous Counters

Asynchronous Counters. Asynchronous Counters Counters and State Machine Design November 25 Asynchronous Counters ENGI 25 ELEC 24 Asynchronous Counters The term Asynchronous refers to events that do not occur at the same time With respect to counter

More information

Flip-Flops, Registers, Counters, and a Simple Processor

Flip-Flops, Registers, Counters, and a Simple Processor June 8, 22 5:56 vra235_ch7 Sheet number Page number 349 black chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor 7. Ng f3, h7 h6 349 June 8, 22 5:56 vra235_ch7 Sheet number 2 Page number

More information

CSE140: Components and Design Techniques for Digital Systems

CSE140: Components and Design Techniques for Digital Systems CE4: Components and esign Techniques for igital ystems Tajana imunic osing ources: Where we are now What we ve covered so far (Chap -5, App. A& B) Number representations Boolean algebra OP and PO Logic

More information

ASYNCHRONOUS COUNTERS

ASYNCHRONOUS COUNTERS LB no.. SYNCHONOUS COUNTES. Introduction Counters are sequential logic circuits that counts the pulses applied at their clock input. They usually have 4 bits, delivering at the outputs the corresponding

More information

L4: Sequential Building Blocks (Flip-flops, Latches and Registers)

L4: Sequential Building Blocks (Flip-flops, Latches and Registers) L4: Sequential Building Blocks (Flip-flops, Latches and Registers) Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified

More information

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas

Take-Home Exercise. z y x. Erik Jonsson School of Engineering and Computer Science. The University of Texas at Dallas Take-Home Exercise Assume you want the counter below to count mod-6 backward. That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count

More information

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.

More information

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements )

Sequential Logic. (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential Logic (Materials taken from: Principles of Computer Hardware by Alan Clements ) Sequential vs. Combinational Circuits Combinatorial circuits: their outputs are computed entirely from their present

More information

Sequential Logic Design Principles.Latches and Flip-Flops

Sequential Logic Design Principles.Latches and Flip-Flops Sequential Logic Design Principles.Latches and Flip-Flops Doru Todinca Department of Computers Politehnica University of Timisoara Outline Introduction Bistable Elements Latches and Flip-Flops S-R Latch

More information

Lecture 8: Synchronous Digital Systems

Lecture 8: Synchronous Digital Systems Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered

More information

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad

EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,

More information

Master/Slave Flip Flops

Master/Slave Flip Flops Master/Slave Flip Flops Page 1 A Master/Slave Flip Flop ( Type) Gated latch(master) Gated latch (slave) 1 Gate Gate GATE Either: The master is loading (the master in on) or The slave is loading (the slave

More information

Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010

Lecture 10 Sequential Circuit Design Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010 EE4800 CMOS igital IC esign & Analysis Lecture 10 Sequential Circuit esign Zhuo Feng 10.1 Z. Feng MTU EE4800 CMOS igital IC esign & Analysis 2010 Sequencing Outline Sequencing Element esign Max and Min-elay

More information

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw. Sequential Circuit Modeling Sequential Elements with Verilog Prof. Chien-Nan Liu TEL: 03-4227151 ext:34534 Email: jimmy@ee.ncu.edu.tw 4-1 Sequential Circuit Outputs are functions of inputs and present states of storage elements

More information

DEPARTMENT OF INFORMATION TECHNLOGY

DEPARTMENT OF INFORMATION TECHNLOGY DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF INFORMATION TECHNLOGY Lab Manual for Computer Organization Lab ECS-453

More information

Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0

Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.

More information

Sequential Logic: Clocks, Registers, etc.

Sequential Logic: Clocks, Registers, etc. ENEE 245: igital Circuits & Systems Lab Lab 2 : Clocks, Registers, etc. ENEE 245: igital Circuits and Systems Laboratory Lab 2 Objectives The objectives of this laboratory are the following: To design

More information

Set-Reset (SR) Latch

Set-Reset (SR) Latch et-eset () Latch Asynchronous Level sensitive cross-coupled Nor gates active high inputs (only one can be active) + + Function 0 0 0 1 0 1 eset 1 0 1 0 et 1 1 0-? 0-? Indeterminate cross-coupled Nand gates

More information

Registers & Counters

Registers & Counters Objectives This section deals with some simple and useful sequential circuits. Its objectives are to: Introduce registers as multi-bit storage devices. Introduce counters by adding logic to registers implementing

More information

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.

Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage

More information

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram

SEQUENTIAL CIRCUITS. Block diagram. Flip Flop. S-R Flip Flop. Block Diagram. Circuit Diagram SEQUENTIAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm Copyright tutorialspoint.com The combinational circuit does not use any memory. Hence the previous

More information

Lecture-3 MEMORY: Development of Memory:

Lecture-3 MEMORY: Development of Memory: Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,

More information

Timing Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency

Timing Methodologies (cont d) Registers. Typical timing specifications. Synchronous System Model. Short Paths. System Clock Frequency Registers Timing Methodologies (cont d) Sample data using clock Hold data between clock cycles Computation (and delay) occurs between registers efinition of terms setup time: minimum time before the clocking

More information

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation

More information

Chapter 9 Latches, Flip-Flops, and Timers

Chapter 9 Latches, Flip-Flops, and Timers ETEC 23 Programmable Logic Devices Chapter 9 Latches, Flip-Flops, and Timers Shawnee State University Department of Industrial and Engineering Technologies Copyright 27 by Janna B. Gallaher Latches A temporary

More information

Cascaded Counters. Page 1 BYU

Cascaded Counters. Page 1 BYU Cascaded Counters Page 1 Mod-N Counters Generally we are interested in counters that count up to specific count values Not just powers of 2 A mod-n counter has N states Counts from 0 to N-1 then rolls

More information

Operating Manual Ver.1.1

Operating Manual Ver.1.1 4 Bit Binary Ripple Counter (Up-Down Counter) Operating Manual Ver.1.1 An ISO 9001 : 2000 company 94-101, Electronic Complex Pardesipura, Indore- 452010, India Tel : 91-731- 2570301/02, 4211100 Fax: 91-731-

More information

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs.

So far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. equential Logic o far we have investigated combinational logic for which the output of the logic devices/circuits depends only on the present state of the inputs. In sequential logic the output of the

More information

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

More information

Theory of Logic Circuits. Laboratory manual. Exercise 3

Theory of Logic Circuits. Laboratory manual. Exercise 3 Zakład Mikroinformatyki i Teorii Automatów yfrowych Theory of Logic ircuits Laboratory manual Exercise 3 Bistable devices 2008 Krzysztof yran, Piotr zekalski (edt.) 1. lassification of bistable devices

More information

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential

More information

74F168*, 74F169 4-bit up/down binary synchronous counter

74F168*, 74F169 4-bit up/down binary synchronous counter INTEGRATED CIRCUITS 74F168*, * Discontinued part. Please see the Discontinued Product List in Section 1, page 21. 1996 Jan 5 IC15 Data Handbook FEATURES Synchronous counting and loading Up/Down counting

More information

7. Latches and Flip-Flops

7. Latches and Flip-Flops Chapter 7 Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The

More information

Combinational Logic Design Process

Combinational Logic Design Process Combinational Logic Design Process Create truth table from specification Generate K-maps & obtain logic equations Draw logic diagram (sharing common gates) Simulate circuit for design verification Debug

More information

CHAPTER 11: Flip Flops

CHAPTER 11: Flip Flops CHAPTER 11: Flip Flops In this chapter, you will be building the part of the circuit that controls the command sequencing. The required circuit must operate the counter and the memory chip. When the teach

More information

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161

More information

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 CDA 3200 Digital Systems Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012 Outline SR Latch D Latch Edge-Triggered D Flip-Flop (FF) S-R Flip-Flop (FF) J-K Flip-Flop (FF) T Flip-Flop

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: ELEMENTARY SEUENTIAL CIRCUITS: FLIP-FLOPS 1st year BSc course 2nd (Spring) term 2012/2013 1

More information

CpE358/CS381. Switching Theory and Logical Design. Class 10

CpE358/CS381. Switching Theory and Logical Design. Class 10 CpE358/CS38 Switching Theory and Logical Design Class CpE358/CS38 Summer- 24 Copyright 24-373 Today Fundamental concepts of digital systems (Mano Chapter ) Binary codes, number systems, and arithmetic

More information

Fig1-1 2-bit asynchronous counter

Fig1-1 2-bit asynchronous counter Digital electronics 1-Sequential circuit counters Such a group of flip- flops is a counter. The number of flip-flops used and the way in which they are connected determine the number of states and also

More information

Decimal Number (base 10) Binary Number (base 2)

Decimal Number (base 10) Binary Number (base 2) LECTURE 5. BINARY COUNTER Before starting with counters there is some vital information that needs to be understood. The most important is the fact that since the outputs of a digital chip can only be

More information

Lecture 10: Sequential Circuits

Lecture 10: Sequential Circuits Introduction to CMOS VLSI esign Lecture 10: Sequential Circuits avid Harris Harvey Mudd College Spring 2004 Outline q Sequencing q Sequencing Element esign q Max and Min-elay q Clock Skew q Time Borrowing

More information

CS311 Lecture: Sequential Circuits

CS311 Lecture: Sequential Circuits CS311 Lecture: Sequential Circuits Last revised 8/15/2007 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

More information

1-800-831-4242

1-800-831-4242 Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description

More information

Lecture 11: Sequential Circuit Design

Lecture 11: Sequential Circuit Design Lecture 11: Sequential Circuit esign Outline Sequencing Sequencing Element esign Max and Min-elay Clock Skew Time Borrowing Two-Phase Clocking 2 Sequencing Combinational logic output depends on current

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

Design Verification & Testing Design for Testability and Scan

Design Verification & Testing Design for Testability and Scan Overview esign for testability (FT) makes it possible to: Assure the detection of all faults in a circuit Reduce the cost and time associated with test development Reduce the execution time of performing

More information

Digital Fundamentals. Lab 8 Asynchronous Counter Applications

Digital Fundamentals. Lab 8 Asynchronous Counter Applications Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives:

More information

Sequential Circuit Design

Sequential Circuit Design Sequential Circuit Design Lan-Da Van ( 倫 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines

More information

Layout of Multiple Cells

Layout of Multiple Cells Layout of Multiple Cells Beyond the primitive tier primitives add instances of primitives add additional transistors if necessary add substrate/well contacts (plugs) add additional polygons where needed

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED DIGITAL TECHNICS II Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 5. LECTURE: REGISTERS AND RELATED 2nd (Spring) term 22/23 5. LECTURE: REGISTERS. Storage registers 2. Shift

More information

Digital Fundamentals

Digital Fundamentals igital Fundamentals with PL Programming Floyd Chapter 9 Floyd, igital Fundamentals, 10 th ed, Upper Saddle River, NJ 07458. All Rights Reserved Summary Latches (biestables) A latch is a temporary storage

More information

(Refer Slide Time: 00:01:16 min)

(Refer Slide Time: 00:01:16 min) Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6

More information

A New Paradigm for Synchronous State Machine Design in Verilog

A New Paradigm for Synchronous State Machine Design in Verilog A New Paradigm for Synchronous State Machine Design in Verilog Randy Nuss Copyright 1999 Idea Consulting Introduction Synchronous State Machines are one of the most common building blocks in modern digital

More information

Napier University. School of Engineering. Electronic Engineering A Module: SE42205 Digital Design

Napier University. School of Engineering. Electronic Engineering A Module: SE42205 Digital Design Napier University School of Engineering Digital Design Clock + U1 out 5V "1" "2" "4" JK-FF D JK-FF C JK-FF B U8 SN7408 signal U4 SN74107 U5 SN74107 U6 SN74107 U3 SN7408 U2 J Q J Q & J Q & K CQ K CQ K CQ

More information

Chapter 5. Sequential Logic

Chapter 5. Sequential Logic Chapter 5 Sequential Logic Sequential Circuits (/2) Combinational circuits: a. contain no memory elements b. the outputs depends on the current inputs Sequential circuits: a feedback path outputs depends

More information

Wiki Lab Book. This week is practice for wiki usage during the project.

Wiki Lab Book. This week is practice for wiki usage during the project. Wiki Lab Book Use a wiki as a lab book. Wikis are excellent tools for collaborative work (i.e. where you need to efficiently share lots of information and files with multiple people). This week is practice

More information

EXPERIMENT 8. Flip-Flops and Sequential Circuits

EXPERIMENT 8. Flip-Flops and Sequential Circuits EXPERIMENT 8. Flip-Flops and Sequential Circuits I. Introduction I.a. Objectives The objective of this experiment is to become familiar with the basic operational principles of flip-flops and counters.

More information

ECE124 Digital Circuits and Systems Page 1

ECE124 Digital Circuits and Systems Page 1 ECE124 Digital Circuits and Systems Page 1 Chip level timing Have discussed some issues related to timing analysis. Talked briefly about longest combinational path for a combinational circuit. Talked briefly

More information

The components. E3: Digital electronics. Goals:

The components. E3: Digital electronics. Goals: E3: Digital electronics Goals: Basic understanding of logic circuits. Become familiar with the most common digital components and their use. Equipment: 1 st. LED bridge 1 st. 7-segment display. 2 st. IC

More information

Design: a mod-8 Counter

Design: a mod-8 Counter Design: a mod-8 Counter A mod-8 counter stores a integer value, and increments that value (say) on each clock tick, and wraps around to 0 if the previous stored value was 7. So, the stored value follows

More information

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1

Clocking. Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 Clocks 1 ing Figure by MIT OCW. 6.884 - Spring 2005 2/18/05 L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle 6.884 - Spring 2005 2/18/05

More information

Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots

Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots Lecture 12: More on Registers, Multiplexers, Decoders, Comparators and Wot- Nots Registers As you probably know (if you don t then you should consider changing your course), data processing is usually

More information

ENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28.

ENEE 244 (01**). Spring 2006. Homework 5. Due back in class on Friday, April 28. ENEE 244 (01**). Spring 2006 Homework 5 Due back in class on Friday, April 28. 1. Fill up the function table (truth table) for the following latch. How is this latch related to those described in the lectures

More information

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation

More information

Lab 1: Study of Gates & Flip-flops

Lab 1: Study of Gates & Flip-flops 1.1 Aim Lab 1: Study of Gates & Flip-flops To familiarize with circuit implementations using ICs and test the behavior of different logic gates and Flip-flops. 1.2 Hardware Requirement a. Equipments -

More information

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs

Sequential Circuits. Combinational Circuits Outputs depend on the current inputs Principles of VLSI esign Sequential Circuits Sequential Circuits Combinational Circuits Outputs depend on the current inputs Sequential Circuits Outputs depend on current and previous inputs Requires separating

More information

Modeling Latches and Flip-flops

Modeling Latches and Flip-flops Lab Workbook Introduction Sequential circuits are digital circuits in which the output depends not only on the present input (like combinatorial circuits), but also on the past sequence of inputs. In effect,

More information

74AC191 Up/Down Counter with Preset and Ripple Clock

74AC191 Up/Down Counter with Preset and Ripple Clock 74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature

More information