# Counters & Shift Registers Chapter 8 of R.P Jain

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1 Chapter 3 Counters & Shift Registers Chapter 8 of R.P Jain

2 Counters & Shift Registers Counters, Syllabus Design of Modulo-N ripple counter, Up-Down counter, design of synchronous counters with and without lockout conditions, Ripple design of shift registers with shift-left, shift-right & parallel load facilities, Universal shift Registers.

3 Counters

4 Counters Counters are sequential circuits which "count" through a specific sequence. They can count up, count down, or count through other fixed sequences. modulus of a counter = no. of states in the cycle A counter with m states is called a modulus-m counter or a divide-by-m counter Types of counters: 1. Ripple Counters or Asynchronous Counter flip-flops connected in cascade clock connected to LSB bit flip-flop Output of this flip flop is clock to next flip flop Output change is delayed more for each bit toward the MSB. 2. Synchronous Counters Clock is connected directly to all the flip-flop Hence output of all flip flops changes simultaneously

5 3 bit ripple counter using T flip flops This is called as a ripple counter due to the way the FFs respond one after another in a kind of rippling effect. 5

6 Note 1.Here T ff is used and is connected to logic 1 as this will toggle at clock edge 2.JK flip flop can be used with J=K= 1 3.To count from , 3 flip flops are required i.e no of flip flops = no of bits 4.Here counter counts from decimal 0 to 8, i.e 8 states (modulo 8) and 3 ff are used i.e 2 no of flip flops = no of states 5.For modulo n counter, N ff are required Where n=2 N 6. If clock period is T, then clock period of 1 st ff is 2T, next has 4T and so on. 7. Q is connected to +ve clock of next ff 8. Propagation delay adds up from LSB-ff to MSB-ff

7 Up-Down counter UP COUNTER: counts from Q is connected to +ve clock of next ff (as in previous slide) Or, Q is connected to -ve clock of next ff DOWN COUNTER: counts from Q is connected to +ve clock of next ff (as in previous slide) Or, Q is connected to -ve clock of next ff

8 Design problems 1. Design a modulo 16 ( ) counter using JK flip flops. 2. Design a modulo 4 down counter It will count 4 states i.e 3,2,1,0 3. Design ripple decade counter (mod-10) -Here at count decimal 10 i.e at 1010, OR the output of all the four flip flops and put this ORed output to clear of all flip flops. This will make next output as 0000.

9 Synchronous Counter Clock is connected directly to all the flip-flop Hence all outputs change simultaneously So, Propagation delay of all flip flops is same

10 2-bit Synchronous Counter

11 Steps : Design of synchronous counter Design a 3 bit synchronous counter Step1 : Draw the State Table

12 Step 2. Prepare State Table Step 3. Choose the flip flops As it is 3 bit, so 3 flip flops are used. We can use either T ff or JK ff only

13 Step 4: Write the excitation table for the flip flop Q n Q n+1 T Q n Q n+1 J K X x 1 0 x x 0 Q n Q n+1 D

14 Step 5: From the excitation table of chosen flip flop, make excitation table for the state table Present State Nxt state J 2 K J 1 K 1 J 0 K 0 Q 2 Q 1 Q 0 Q 2 Q 1 Q X 0 X 1 x X 0 x x X x 0 1 x x x 1 x x 0 0 X 1 x x 0 0 x x x 0 x 0 1 x x 1 x 1 x 1

15 Step 6: Using K map, find equations for J 0, K 0, J 1, K 1,J 2, K 2 We get: J 0 = K 0 =1 J 1 = K 1 =Q 0 J 2 = K 2 =Q 0 Q 1

16 3 bit synchronous counter Step 7: Draw circuit diagram

17 Design Problem 1.Design 4-bit synchronous up-counter 2.Design 4-bit synchronous down-counter using T-ff

18 Design Problem 3.Design synchronous decade counter (mod-10) (counts from 0 9 and resets to 0) 4. Design a synchronous counter which counts as and so on 5. Design Mod 7 counter. 6. Design a 3bit up-down counter Hint: Include a direction control bit M. If M=0, it acts as up counter and when M=1, it acts as down counter. For 3 bit we have 8 states, but because of M, we will have 16 states {eg 8.10 R.P Jain Pg 260}

19 7.Design sync counter for state diagram using D ff

20 Soln

21 8. 7.Design sync counter for state diagram

22 9.Design sync counter for state diagram

23 Lockout condition 10.Design a synchronous counter for using JK flip flop. Avoid lockout condition Here, state 5, 2, 0 are forced to some specified state. This is called avoiding lock-out condition. If next states of 5,2,0 is not specified, then foe example next state of 5 was 2 then the counter would have been locked.

24 Shift Registers

25 Last Lecture flip flops hold data bit A data input value is loaded into the register on the rise of the clock edge. Some circuits have additional ~clear or ~reset inputs. D C Q Q Positive edgetriggered flip-flop C D Q ? Qn

26 Four bit Register D0 clk D Q C Q0 D1 D Q Q1 D0 Q0 C D1 Q1 D2 D Q Q2 D2 Q2 D3 C D Q Q3 D3 clk Q3 C Circuit Symbol

27 Shift Registers Allow stored data to be moved from one bit position to another Q a Q b Q c Q d D a D Q D Q D Q D Q C C C C A B C D D a =1: Initial Values after clock 1 after clock 2 D a = 0: after clock 3 after clock 4 after clock 5 Q a Q b Q c Q d

28 Shift Registers Points to note: At every clock pulse, the first flip flop is loaded with the value of the data in stream The data that was in this flip flop is then loaded into the second and so on. The data can be taken out of the last flip flop in serial form or it can be taken from all outputs at the same time parallel form.

29 Shift Left/Right Registers Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle)

30 Types of Shift Registers Shift registers can be loaded using parallel/serial input lines.therefore inputs can be parallel or serial Outputs can be parallel or serial Functions that shift registers can carry out include: Serial in, serial out shift register Serial in, parallel out shift register Parallel in, serial out shift register Parallel in, parallel out shift register

31 Serial-In Serial-Out shift register

32 Serial-In Parallel-Out shift register

33 Parallel-In Serial-Out shift register

34 Parallel-In Parallel-Out shift register

35

36

37 Ring Counter Ring counter: is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Typically a pattern consisting of a single 1 bit is circulated, so the state repeats every N clock cycles if N flip-flops are used. It can be used as a cycle counter of N states. Johnson counter: is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage..

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