Latches, the D Flip-Flop & Counter Design. ECE 152A Winter 2012
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1 Latches, the D Flip-Flop & Counter Design ECE 52A Winter 22
2 Reading Assignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7. Basic Latch 7.2 Gated SR Latch 7.2. Gated SR Latch with NAND Gates 7.3 Gated D Latch 7.3. Effects of Propagation Delays February 6, 22 ECE 52A - Digital Design Principles 2
3 Reading Assignment Brown and Vranesic (cont) 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) 7.4 Master-Slave and Edge-Triggered D Flip-Flops 7.4. Master-Slave D Flip-Flop Edge-Triggered D Flip-Flop D Flip-Flop with Clear and Preset Flip-Flop Timing Parameters (2 nd edition) February 6, 22 ECE 52A - Digital Design Principles 3
4 Reading Assignment Roth Latches and Flip-Flops. Introduction.2 Set-Reset Latch.3 Gated D Latch.4 Edge-Triggered D Flip-Flop February 6, 22 ECE 52A - Digital Design Principles 4
5 Reading Assignment Roth (cont) 2 Registers and Counters 2. Registers and Register Transfers 2.2 Shift Registers 2.3 Design of Binary Counters 2.4 Counters for Other Sequences February 6, 22 ECE 52A - Digital Design Principles 5
6 Combinational vs. Sequential Logic Combinational logic Function of present inputs only Output is known if inputs (some or all) are known Sequential logic Function of past and present inputs Memory or state Output known if present input and present state are known Initial conditions often unknown (or undefined) February 6, 22 ECE 52A - Digital Design Principles 6
7 Gate Delays Recall from earlier lecture When gate inputs change, outputs don t change instantaneously February 6, 22 ECE 52A - Digital Design Principles 7
8 Feedback Outputs connected to inputs Single inverter feedback If propagation delay is long enough, output will oscillate February 6, 22 ECE 52A - Digital Design Principles 8
9 Feedback If the propagation delay is not long enough, the output will settle somewhere in the middle V in = V out February 6, 22 ECE 52A - Digital Design Principles 9
10 Feedback Ring Oscillator Any odd number of inverters will oscillate ½ period = total prop delay of chain February 6, 22 ECE 52A - Digital Design Principles
11 Feedback What about an even number of inversions? Two inverter feedback Memory (or State) Static or stored in memory February 6, 22 ECE 52A - Digital Design Principles
12 The Latch Replace inverters with NOR gates February 6, 22 ECE 52A - Digital Design Principles 2
13 The Set-Reset (SR) Latch NOR implementation Inverted feedback February 6, 22 ECE 52A - Digital Design Principles 3
14 The SR Latch R = Reset (clear) Q, Q* S = Set (preset) Q, Q* NOR gate implementation Either input = forces an output to February 6, 22 ECE 52A - Digital Design Principles 4
15 The SR Latch (cont) Terminology Present state, Q Current value of Q and Q* Next state, Q + Final value of Q and Q* after input changes February 6, 22 ECE 52A - Digital Design Principles 5
16 The SR Latch (cont) Operation S=, R= : set to, Q + = S=, R= : reset to, Q + = S=, R= : hold state, Q + = Q S=, R= : not allowed Q + = Q* + =, lose state February 6, 22 ECE 52A - Digital Design Principles 6
17 The SR Latch (cont) Timing Diagram RS inputs are pulses Temporarily high, but normally low February 6, 22 ECE 52A - Digital Design Principles 7
18 The SR Latch (cont) Characteristic Equation Algebraic expression of flip-flop behavior Plot characteristic table on map, find Q + Q + = S + R Q (S = R = not allowed) February 6, 22 ECE 52A - Digital Design Principles 8
19 The SR Latch (cont) Characteristic Equation Q + = S + R Q (S = R = not allowed) Q becomes when S =, R = Stays Q when S = R = Q becomes when S =, R = February 6, 22 ECE 52A - Digital Design Principles 9
20 The SR Latch (cont) State Table NS (Q + ) PS (Q) SR= X X February 6, 22 ECE 52A - Digital Design Principles 2
21 The SR Latch (cont) State Diagram SR = SR = X SR = X SR = February 6, 22 ECE 52A - Digital Design Principles 2
22 The SR Latch with NANDS NAND Based S R Latch S = R = not allowed Either input = forces output to February 6, 22 ECE 52A - Digital Design Principles 22
23 The Gated SR Latch Also known as transparent latch Output follows input (transparent) when enabled February 6, 22 ECE 52A - Digital Design Principles 23
24 The Gated SR Latch (cont) Timing Diagram February 6, 22 ECE 52A - Digital Design Principles 24
25 The Gated SR Latch (cont) NAND Implementation February 6, 22 ECE 52A - Digital Design Principles 25
26 The Gated Data (D) Latch NAND Implementation of transparent D latch February 6, 22 ECE 52A - Digital Design Principles 26
27 The Gated D Latch Timing Diagram February 6, 22 ECE 52A - Digital Design Principles 27
28 The Edge Triggered D Flip-Flop The D Flip-Flop Input D, latched and passed to Q on clock edge Rising edge triggered or falling edge triggered Characteristic table and function February 6, 22 ECE 52A - Digital Design Principles 28
29 The Edge Triggered D Flip-Flop Most commonly used flip-flop Output follows input after clock edge Q and Q* change only on clock edge Timing diagram for negative edge triggered flip-flop February 6, 22 ECE 52A - Digital Design Principles 29
30 The D Flip-Flop State Table PS (Q) NS (Q + ) D = D = February 6, 22 ECE 52A - Digital Design Principles 3
31 The D Flip-Flop (cont) State Diagram D = D = D = D = February 6, 22 ECE 52A - Digital Design Principles 3
32 The Master-Slave D Flip-Flop Construct edge triggered flip-flop from 2 transparent latches Many other topologies for edge triggered flip-flops Falling edge triggered (below) February 6, 22 ECE 52A - Digital Design Principles 32
33 The Master-Slave D Flip-Flop (cont) Timing Diagram Falling edge triggered February 6, 22 ECE 52A - Digital Design Principles 33
34 The Master-Slave D Flip-Flop (cont) A Second Timing Diagram Rising edge triggered February 6, 22 ECE 52A - Digital Design Principles 34
35 The Edge Triggered D Flip-Flop True Edge Triggered D Flip-Flop Never transparent (unlike Master Slave) February 6, 22 ECE 52A - Digital Design Principles 35
36 The Edge Triggered D Flip-Flop Operation of Flip-Flop February 6, 22 ECE 52A - Digital Design Principles 36
37 Types of D Flip-Flops Gated, Positive Edge and Negative Edge February 6, 22 ECE 52A - Digital Design Principles 37
38 Timing Parameters CLK Q Delay from clock edge (CLK) to valid (Q, Q*) output Setup time t su Stable, valid data (D) before clock edge (CLK) Hold time t hold Stable, valid data (D) after clock edge (CLK) February 6, 22 ECE 52A - Digital Design Principles 38
39 Maximum Frequency Maximum frequency (minimum clock period) for a digital system CLK Q + propagation delay + t su February 6, 22 ECE 52A - Digital Design Principles 39
40 Counter Design with D Flip-Flops Design Example #: Modulo 3 counter Requires 2 flip-flops One for each state variable February 6, 22 ECE 52A - Digital Design Principles 4
41 Counter Design with D Flip-Flops State Diagram Transitions on clock edge February 6, 22 ECE 52A - Digital Design Principles 4
42 Counter Design with D Flip-Flops State Table PS NS A B A + B + X X February 6, 22 ECE 52A - Digital Design Principles 42
43 Counter Design with D Flip-Flops Next State Maps A B A B X X A + = B B + = A B February 6, 22 ECE 52A - Digital Design Principles 43
44 Counter Design with D Flip-Flops Implementation with D Flip-Flops What are the D inputs to flip-flops A and B? Recall characteristic equation for D flip-flop Q + = D Therefore, A + = B D A = B and B + = A B D B = A B February 6, 22 ECE 52A - Digital Design Principles 44
45 Counter Design with D Flip-Flops Implementation with positive edge triggered flip-flops February 6, 22 ECE 52A - Digital Design Principles 45
46 Counter Design with D Flip-Flops Implementation with positive edge triggered flip-flops Timing diagram February 6, 22 ECE 52A - Digital Design Principles 46
47 Counter Design with D Flip-Flops Design Example #2: Modulo 3 counter with up/down* input Counter counts up with input = and down with input = Implement with D flip-flops February 6, 22 ECE 52A - Digital Design Principles 47
48 Counter Design with D Flip-Flops State diagram February 6, 22 ECE 52A - Digital Design Principles 48
49 February 6, 22 ECE 52A - Digital Design Principles 49 Counter Design with D Flip-Flops State table X X X X B + A + B A U
50 Counter Design with D Flip-Flops Next state maps and flip-flop inputs U AB U AB X X X X A + = D A = UB + U A B B + = D B = U A + UA B February 6, 22 ECE 52A - Digital Design Principles 5
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