NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

Transcription

1 PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6 Binary Counter. State changes of the counters are synchronous with the LOW-to-HIGH traition of the Clock Pulse input. An asynchronous Parallel Load () input overrides counting and loads the data present on the Pn inputs into the flip-flops, which makes it possible to use the circuits as programmable counters. A Count Enable () input serves as the carry/borrow input in multi-stage counters. An Up/Down Count Control () input determines whether a circuit counts up or down. A Terminal Count (TC) output and a Ripple Clock () output provide overflow/underflow indication and make possible a variety of methods for generating carry/ borrow signals in multistage counter applicatio. Low Power mw Typical Dissipation High Speed MHz Typical Count Frequency Synchronous Counting Asynchronous Parallel Load Individual Preset Inputs Count Enable and Up/Down Control Inputs Cascadable Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC P0 TC P2 P P Q Q0 Q2 Q3 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. SN54/74LS90 SN54/74LS9 PRESETTABLE BCD/ DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS 6 6 LOW POWER SCHOTTKY 6 J SUFFIX RAMIC CASE N SUFFIX ASTIC CASE ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 5 0 D SUFFIX SOIC CASE 75B-03 9 PIN NAMES LOADING (Note a) HIGH LOW U /D Pn Qn Count Enable (Active LOW) Input Clock Pulse (Active HIGH going edge) Input Up/Down Count Control Input Parallel Load Control (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Ripple Clock Output (Note b) Terminal Count Output (Note b).5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0 U.L. 0 U.L. 0 U.L. 0.7 U.L U.L U.L U.L U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 (2.5) U.L. TC NOTES: a. TTL Unit Load (U.L.) = 40 µa HIGH/.6 ma LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges P0 P P2 Q0 Q VCC = PIN 6 GND = PIN 8 P3 TC Q2 Q

2 STATE DIAGRAMS UP: DOWN: LS90 TC = Q0 Q3 () TC = Q0 Q Q2 Q3 () UP: DOWN: LS9 TC = Q0 Q Q2 Q3 () TC = Q0 Q Q2 Q3 () COUNT UP COUNT DOWN LS90 LS9 LOGIC DIAGRAMS P0 P P2 P TC Q0 Q Q2 Q3 VCC = PIN 6 GND = PIN 8 = PIN NUMBERS DECADE COUNTER LS90 5-2

3 LOGIC DIAGRAMS (continued) P0 P P2 P TC Q0 Q Q2 Q3 VCC = PIN 6 GND = PIN 8 = PIN NUMBERS BINARY COUNTER LS9 5-3

4 FUNCTIONAL DESCRIPTION The LS90 is a synchronous Up/ Down BCD Decade Counter and the LS9 is a synchronous Up/Down 4-Bit Binary Counter. The operating modes of the LS90 decade counter and the LS9 binary counter are identical, with the only difference being the count sequences as noted in the state diagrams. Each circuit contai four master/ slave flip-flops, with internal gating and steering logic to provide individual preset, count-up and count-down operatio. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load () input is LOW, information present on the Parallel Data inputs (P0 P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functio, as indicated in the Mode Select Table. A HIGH signal on the input inhibits counting. When is LOW, internal state change are initiated synchronously by the LOW-to-HIGH traition of the clock input. The direction of counting is determined by the input signal, as indicated in the Mode Select Table. When counting is to be enabled, the signal can be made LOW when the clock is in either state. However, when counting is to be inhibited, the LOW-to-HIGH traition must occur only while the clock is HIGH. Similarly, the signal should only be changed when either or the clock is HIGH. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches maximum (9 for the LS90, 5 for the LS9) in the count-up mode. The TC output will then remain HIGH until a state change occurs, whether by counting or presetting or until is changed. The TC output should not be used as a clock signal because it is subject to decoding spikes. The TC signal is also used internally to enable the Ripple Clock () output. The output is normally HIGH. When is LOW and TC is HIGH, the output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again. This feature simplifies the design of multi-stage counters, as indicated in Figures a and b. In Figure a, each output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited drive capability, since it drives only the first stage. To prevent counting in all stages it is only necessary to inhibit the first stage, since a HIGH signal on inhibits the output pulse, as indicated in the Truth Table. A disadvantage of this configuration, in some applicatio, is the timing skew between state changes in the first and last stages. This represents the cumulative delay of the clock as it ripples through the preceding stages. A method of causing state changes to occur simultaneously in all stages is shown in Figure b. All clock inputs are driven in parallel and the outputs propagate the carry/ borrow signals in ripple fashion. In this configuration the LOW state duration of the clock must be long enough to allow the negative-going edge of the carry/ borrow signal to ripple through to the last stop before the clock goes HIGH. There is no such restriction on the HIGH state duration of the clock, since the output of any package goes HIGH shortly after its input goes HIGH. The configuration shown in Figure c avoids ripple delays and their associated restrictio. The input signal for a given stage is formed by combining the TC signals from all the preceding stages. Note that in order to inhibit counting an enable signal must be included in each carry gate. The simple inhibit scheme of Figures a and b doesn t apply, because the TC output of a given stage is not affected by its own. MODE SELECT TABLE INPUTS U /D MODE H L L Count Up H L H Count Down L X X X Preset (Asyn.) H H X X No Change (Hold) TRUTH TABLE INPUTS TC* OUTPUT L H H X X H X L X H * TC is generated internally L = LOW Voltage Level H = HIGH Voltage Level X = Don t Care = LOW-to-HIGH Clock Traition = LOW Pulse 5-4

5 GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage V TA Operating Ambient Temperature Range C IOH Output Current High 54, ma IOL Output Current Low ma DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditio i VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage V Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage V VCC = MIN, IIN = 8 ma VOH VOL Output HIGH Voltage Output LOW Voltage V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table 54, V IOL = 4.0 ma VCC = VCC MIN, VIN =VIL or VIH V IOL = 8.0 ma per Truth Table IIH Input HIGH Current Other Inputs Other Inputs µa VCC = MAX, VIN = 2.7 V ma VCC = MAX, VIN = 7.0 V IIL Input LOW Current Other Inputs IOS Short Circuit Current (Note ) ma VCC = MAX ICC Power Supply Current 35 ma VCC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. ma VCC = MAX, VIN = 0.4 V 5-5

6 AC CHARACTERISTICS (TA = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditio i fmax Maximum Clock Frequency MHz Propagation Delay, to Output Q Data to Output Q Clock to Clock to Output Q Clock to TC VCC = 5.0 V CL = 5 pf U / D to U / D to TC 2 22 to 2 22 AC SETUP REQUIREMENTS (TA = 25 C) Symbol Parameter Min Limits Typ Max Unit Test Conditio i tw Pulse Width 25 tw Pulse Width 35 ts Data Setup Time 20 VCC = 5.0 V th Data Hold Time 5.0 trec Recovery Time 40 DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock traition from LOW-to-HIGH in order to be recognized and traferred to the outputs. HOLD TIME (th) is defined as the minimum time following the clock traition from LOW-to-HIGH that the logic level must be maintained at the input in order to eure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock traition from LOWto-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock traition from LOW-to-HIGH in order to recognize and trafer HIGH data to the Q outputs. 5-6

7 DIRECTION CONTROL ENABLE CLOCK Figure a. n-stage Counter Using Ripple Clock DIRECTION CONTROL ENABLE CLOCK Figure b. Synchronous n-stage Counter Using Ripple Carry/ Borrow DIRECTION CONTROL ENABLE TC TC TC CLOCK Figure c. Synchronous n-stage Counter with Parallel Gated Carry/ Borrow 5-7

8 AC WAVEFORMS /f MAX tw OR Q OR TC Figure Figure 2 Pn Pn tw Qn NOTE: = LOW Qn Figure 3 Figure 4 Pn tw trec ts(h) th(h) ts(l) th(l) Q Figure 5 Figure 6 Qn Q = P Q = P * The shaded areas indicate when the input is permitted * to change for predictable output performance th(l) th(h) TC ts(l) ts(h) MAY CHANGE (H-L) only MAY CHANGE Figure 7 Figure 8 5-8