74F168*, 74F169 4-bit up/down binary synchronous counter

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1 INTEGRATED CIRCUITS 74F168*, * Discontinued part. Please see the Discontinued Product List in Section 1, page Jan 5 IC15 Data Handbook

2 FEATURES Synchronous counting and loading Up/Down counting Modulo 16 binary counter Two Count Enable inputs for n-bit cascading Positive edge-triggered clock Built-in carry look-ahead capability Presettable for programmable operation DESCRIPTION The is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applicatio in high-speed counting desig. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when itructed by the Count Enable inputs and internal gating. This mode of operation eliminates the output spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the flip-flops on the Low-to-High traition of the clock. The counter is fully programmable; that is, the outputs may be preset to either level. Presetting is synchronous with the clock and takes place regardless of the levels of the Count Enable inputs. A Low level on the Parallel Enable () input disables the counter and causes the data at the D n input to be loaded into the counter on the next Low-to-High traition of the clock. PIN CONFIGURATION D D 1 D 2 D 3 GND 1 16 V CC Q Q 1 Q 2 Q 3 SF766 TY TYPICAL f MAX SUPPLY CURRENT TYPICAL (TOTAL) 115MHz 35mA ORDERING INFORMATION DESCRIPTION ORDER CODE COMMERCIAL RANGE V CC = 5V ±1%, T amb = C to +7 C PKG DWG # 16-pin plastic DIP NN SOT pin plastic SO ND SOT19-1 The direction of counting is controlled by the Up/Down () input; a High will cause the count to increase, a Low will cause the count to decrease. The carry look-ahead circuitry provides for n-bit synchronous applicatio without additional gating. Itrumental in accomplishing this function are two Count Enable inputs (, ) and a Terminal Count () output. Both Count Enable inputs must be Low to count. The input is fed forward to enable the output. The output thus enabled will produce a Low output pulse with a duration approximately equal to the High level portion of the Q output. The Low level pulse is used to enable successive cascaded stages. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D - D 3 Parallel data inputs 1./1. 2µA/.6mA Count Enable parallel input (active Low) 1./1. 2µA/.6mA Count Enable Trickle input (active Low) 1./2. 2µA/1.2mA Clock input (active rising edge) 1./1. 2µA/.6mA Parallel Enable input (active Low) 1./1. 2µA/.6mA Up/Down count control input 1./1. 2µA/.6mA Q - Q 3 Flip-flop outputs 5/33 1.mA/2mA Terminal count output (active Low) 5/33 1.mA/2mA NOTE: One (1.) FAST Unit Load (U.L.) is defined as: 2µA in the High state and.6ma in the Low state Jan

3 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) CTR DIV 16 M1 [LOAD] 9 D D 1 D 2 D 3 1 M2 [COUNT] M3 [UP] Q Q 1 Q 2 Q M4 [DOWN] G5 G6 2, 3, 5, 6+/C7 2, 4, 5, 6 3, 5 CT=15 4, 5 CT= 15 V CC = Pin 16 GND = Pin SF , 7D [1] [2] [4] [8] SF787 FUNCTIONAL DESCRIPTION The uses edge-triggered J-K-type flip-flops and have no cotraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operatio, as indicated in the Mode Select Table. When is Low, the data on the D - D 3 inputs enter the flip-flops on the next rising edge of the Clock. In order for counting to occur, both and must be Low and must be High; the input determines the direction of counting. The Terminal Count () output is normally High and goes Low, provided that is Low, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The output state is not a function of the Count Enable Parallel () input level. Since the signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on. For this reason the use of as a clock signal is not recommended (see logic equatio below). 1) Count Enable = 2) Up: = Q Q 3 () 3) Down: = Q Q 1 Q 2 Q 3 () MODE SELECT FUNCTION TABLE INPUTS OUTPUTS D n Q n ORATING MODE X X X l l L (1) Parallel load (Dn Qn) X X X X X H (1) h l l h X Count Up (1) Count Up (increment) l l l h X Count Down (1) Count Down (decrement) X h X h X q n (1) Hold (do nothing) X X X h X q n H H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock traition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock traition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock traition X = Don t care = Low-to-High clock traition (1) = The is Low when is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL) Jan 5 3

4 MODE SELECT TABLE INPUTS ORATING MODE STATE DIAGRAM L X X X Load(D n Q n ) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) H = High Voltage L = Low Voltage Level X = Don t care COUNT DOWN COUNT UP SF788 LOGIC DIAGRAM D 3 D Q Q 14 Q D 1 4 D Q Q 13 Q 1 D 2 5 D Q Q 12 Q 2 D 3 6 D Q 9 Q 11 Q V CC = Pin 16 GND = Pin 8 SF Jan 5 4

5 APPLICATION D D 1 D 2 D 3 D D 1 D 2 D 3 D D 1 D 2 D 3 D D 1 D 2 D 3 Q Q 1 Q 2 Q 3 Q Q 1 Q 2 Q 3 Q Q 1 Q 2 Q 3 Q Q 1 Q 2 Q 3 LEAST SIGNIFICANT 4-BIT COUNTER MOST SIGNIFICANT 4-BIT COUNTER SF79 Figure 1. Synchronous Multistage Counting Scheme ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage.5 to +7. V V IN Input voltage.5 to +7. V I IN Input current 3 to +5 ma V OUT Voltage applied to output in High output state.5 to +V CC V I OUT Current applied to output in Low output state 4 ma T amb Operating free-air temperature range to +7 C T STG Storage temperature 65 to +15 C RECOMMENDED ORATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT Min Nom Max V CC Supply voltage V V IH High-level input voltage 2. V V IL Low-level input voltage.8 V I IK Input clamp current 18 ma I OH High-level output current 1 ma I OL Low-level output current 2 ma T amb Operating free-air temperature range 7 C 1996 Jan 5 5

6 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS NO TAG MIN LIMITS TYP NO TAG MAX UNIT V = MIN, V = MAX, ±1%V CC 2.5 V V OH High-level output voltage CC IL V IH = MIN, I OH = MAX ±5%V CC V V = MIN, V = MAX, ±1%V CC.35.5 V V OL Low-level output voltage CC IL V IH = MIN, I OL = MAX ±5%V CC.35.5 V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at maximum input voltage V CC = MAX, V I = 7.V 1 µa I IH High-level input current V CC = MAX, V I = 2.7V 2 µa I IL Low-level input current V CC = MAX, V I =.5V 1.2 ma Others V CC = MAX, V I =.5V.6 ma I OS Short-circuit output current NO TAG V CC = MAX 6 15 ma I CC Supply current (total) 4 V CC = MAX ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 4. I CC is measured after applying a momentary 4.5V, then ground to the clock input with all other inputs grounded and all outputs open Jan 5 6

7 AC ELECTRICAL CHARACTERISTICS LIMITS T amb = +25 C T amb = C to +7 C SYMBOL PARAMETER TEST CONDITIONS V CC = +5V V CC = +5V ± 1% UNIT C L = 5pF, R L = 5Ω C L = 5pF, R L = 5Ω MIN TYP MAX MIN MAX f MAX Maximum clock frequency Waveform MHz Propagation delay to Q n (, High or Low) Propagation delay to Propagation delay to Propagation delay to AC SETUP REQUIREMENTS Waveform 1 Waveform 1 Waveform 2 Waveform 3 LIMITS LIMITS T amb = +25 C T amb = C to +7 C SYMBOL PARAMETER TEST CONDITIONS V CC = +5.V V CC = +5.V ± 1% UNIT C L = 5pF, R L = 5Ω C L = 5pF, R L = 5Ω t h (H) t h (L) t h (H) t h (L) t h (H) t h (L) t h (H) t h (L) t w (H) t w (L) Setup time, High or Low D n to Hold time, High or Low D n to Set-up time, High or Low or to Hold time, High or Low or to Set-up time, High or Low to Hold time, High or Low to Set-up time, High or Low to Hold time, High or Low to U or D pulse width, High or Low Waveform 4 Waveform 4 Waveform 5 Waveform 5 Waveform 4 Waveform 4 Waveform 6 Waveform 6 Waveform MIN TYP MIN MAX Jan 5 7

8 AC WAVEFORMS For all waveforms, = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f MAX t W (H) t W (L) Q n VM SF792 Waveform 2. Propagation Delays Input to Terminal Count Output SF791A Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency D n t s t h t h = t h = n Waveform 3. Propagation Delay Input to Terminal Count Output SF793 Waveform 4. Parallel Data and Parallel Enable Setup and Hold Times SF794 t h (L) t h (H) t h (L) t h (H) n n Q n NO CHANGE COUNT NO CHANGE Q n COUNT DOWN COUNT UP Waveform 5. Count Enable Setup and Hold Times SF795 SF796 Waveform 6. Up/Down Control Setup and Hold Times 1996 Jan 5 8

9 TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences) D D 1 D 2 D 3 and Q Q 1 Q 2 Q 3 SEQUENCE } LOAD COUNT UP INHIBIT COUNT DOWN SF797 NOTES: The operation of the is similar to the Illustration above. 1. Load (preset) to BCD seven 2. Count up to eight, nine (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven TEST CIRCUIT AND WAVEFORM PULSE GENERATOR V IN V CC D.U.T. V OUT NEGATIVE PULSE 9% 1% t THL ( t f ) t w t TLH ( t r ) 1% 9% AMP (V) V R T C L R L Test Circuit for Totem-Pole Outputs POSITIVE PULSE 1% 9% t TLH ( t r ) t w t THL ( t f ) 9% 1% AMP (V) V DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F Input Pulse Definition INPUT PULSE REQUIREMENTS amplitude rep. rate t w t TLH t THL 3.V 1.5V 1MHz SF Jan 5 9

10 74F168*, DIP16: plastic dual in-line package; 16 leads (3 mil) SOT38-4 * Discontinued part. Please see the Discontinued Product List in Section 1, page Jan 5 1

11 74F168*, SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT19-1 * Discontinued part. Please see the Discontinued Product List in Section 1, page Jan 5 11

12 74F168*, DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 349 Sunnyvale, California Telephone Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Date of release: July 1994 Document order number: * Discontinued part. Please see the Discontinued Product List in Section 1, page 21.