74F168*, 74F169 4-bit up/down binary synchronous counter

Save this PDF as:
 WORD  PNG  TXT  JPG

Size: px
Start display at page:

Download "74F168*, 74F169 4-bit up/down binary synchronous counter"

Transcription

1 INTEGRATED CIRCUITS 74F168*, * Discontinued part. Please see the Discontinued Product List in Section 1, page Jan 5 IC15 Data Handbook

2 FEATURES Synchronous counting and loading Up/Down counting Modulo 16 binary counter Two Count Enable inputs for n-bit cascading Positive edge-triggered clock Built-in carry look-ahead capability Presettable for programmable operation DESCRIPTION The is a 4-bit synchronous, presettable Modulo 16 up/down counter featuring an internal carry look-ahead for applicatio in high-speed counting desig. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when itructed by the Count Enable inputs and internal gating. This mode of operation eliminates the output spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the flip-flops on the Low-to-High traition of the clock. The counter is fully programmable; that is, the outputs may be preset to either level. Presetting is synchronous with the clock and takes place regardless of the levels of the Count Enable inputs. A Low level on the Parallel Enable () input disables the counter and causes the data at the D n input to be loaded into the counter on the next Low-to-High traition of the clock. PIN CONFIGURATION D D 1 D 2 D 3 GND 1 16 V CC Q Q 1 Q 2 Q 3 SF766 TY TYPICAL f MAX SUPPLY CURRENT TYPICAL (TOTAL) 115MHz 35mA ORDERING INFORMATION DESCRIPTION ORDER CODE COMMERCIAL RANGE V CC = 5V ±1%, T amb = C to +7 C PKG DWG # 16-pin plastic DIP NN SOT pin plastic SO ND SOT19-1 The direction of counting is controlled by the Up/Down () input; a High will cause the count to increase, a Low will cause the count to decrease. The carry look-ahead circuitry provides for n-bit synchronous applicatio without additional gating. Itrumental in accomplishing this function are two Count Enable inputs (, ) and a Terminal Count () output. Both Count Enable inputs must be Low to count. The input is fed forward to enable the output. The output thus enabled will produce a Low output pulse with a duration approximately equal to the High level portion of the Q output. The Low level pulse is used to enable successive cascaded stages. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D - D 3 Parallel data inputs 1./1. 2µA/.6mA Count Enable parallel input (active Low) 1./1. 2µA/.6mA Count Enable Trickle input (active Low) 1./2. 2µA/1.2mA Clock input (active rising edge) 1./1. 2µA/.6mA Parallel Enable input (active Low) 1./1. 2µA/.6mA Up/Down count control input 1./1. 2µA/.6mA Q - Q 3 Flip-flop outputs 5/33 1.mA/2mA Terminal count output (active Low) 5/33 1.mA/2mA NOTE: One (1.) FAST Unit Load (U.L.) is defined as: 2µA in the High state and.6ma in the Low state Jan

3 LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) CTR DIV 16 M1 [LOAD] 9 D D 1 D 2 D 3 1 M2 [COUNT] M3 [UP] Q Q 1 Q 2 Q M4 [DOWN] G5 G6 2, 3, 5, 6+/C7 2, 4, 5, 6 3, 5 CT=15 4, 5 CT= 15 V CC = Pin 16 GND = Pin SF , 7D [1] [2] [4] [8] SF787 FUNCTIONAL DESCRIPTION The uses edge-triggered J-K-type flip-flops and have no cotraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operatio, as indicated in the Mode Select Table. When is Low, the data on the D - D 3 inputs enter the flip-flops on the next rising edge of the Clock. In order for counting to occur, both and must be Low and must be High; the input determines the direction of counting. The Terminal Count () output is normally High and goes Low, provided that is Low, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The output state is not a function of the Count Enable Parallel () input level. Since the signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on. For this reason the use of as a clock signal is not recommended (see logic equatio below). 1) Count Enable = 2) Up: = Q Q 3 () 3) Down: = Q Q 1 Q 2 Q 3 () MODE SELECT FUNCTION TABLE INPUTS OUTPUTS D n Q n ORATING MODE X X X l l L (1) Parallel load (Dn Qn) X X X X X H (1) h l l h X Count Up (1) Count Up (increment) l l l h X Count Down (1) Count Down (decrement) X h X h X q n (1) Hold (do nothing) X X X h X q n H H = High voltage level steady state h = High voltage level one setup time prior to the Low-to-High clock traition L = Low voltage level steady state l = Low voltage level one setup time prior to the Low-to-High clock traition q = Lower case letters indicate the state of the referenced output prior to the Low-to-High clock traition X = Don t care = Low-to-High clock traition (1) = The is Low when is Low and the counter is at Terminal Count. Terminal Count Up is (HHHH) and Terminal Count Down is (LLLL) Jan 5 3

4 MODE SELECT TABLE INPUTS ORATING MODE STATE DIAGRAM L X X X Load(D n Q n ) H L L H Count Up (Increment) H L L L Count Down (Decrement) H H X X No Change (Hold) H X H X No Change (Hold) H = High Voltage L = Low Voltage Level X = Don t care COUNT DOWN COUNT UP SF788 LOGIC DIAGRAM D 3 D Q Q 14 Q D 1 4 D Q Q 13 Q 1 D 2 5 D Q Q 12 Q 2 D 3 6 D Q 9 Q 11 Q V CC = Pin 16 GND = Pin 8 SF Jan 5 4

5 APPLICATION D D 1 D 2 D 3 D D 1 D 2 D 3 D D 1 D 2 D 3 D D 1 D 2 D 3 Q Q 1 Q 2 Q 3 Q Q 1 Q 2 Q 3 Q Q 1 Q 2 Q 3 Q Q 1 Q 2 Q 3 LEAST SIGNIFICANT 4-BIT COUNTER MOST SIGNIFICANT 4-BIT COUNTER SF79 Figure 1. Synchronous Multistage Counting Scheme ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT V CC Supply voltage.5 to +7. V V IN Input voltage.5 to +7. V I IN Input current 3 to +5 ma V OUT Voltage applied to output in High output state.5 to +V CC V I OUT Current applied to output in Low output state 4 ma T amb Operating free-air temperature range to +7 C T STG Storage temperature 65 to +15 C RECOMMENDED ORATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT Min Nom Max V CC Supply voltage V V IH High-level input voltage 2. V V IL Low-level input voltage.8 V I IK Input clamp current 18 ma I OH High-level output current 1 ma I OL Low-level output current 2 ma T amb Operating free-air temperature range 7 C 1996 Jan 5 5

6 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS NO TAG MIN LIMITS TYP NO TAG MAX UNIT V = MIN, V = MAX, ±1%V CC 2.5 V V OH High-level output voltage CC IL V IH = MIN, I OH = MAX ±5%V CC V V = MIN, V = MAX, ±1%V CC.35.5 V V OL Low-level output voltage CC IL V IH = MIN, I OL = MAX ±5%V CC.35.5 V V IK Input clamp voltage V CC = MIN, I I = I IK V I I Input current at maximum input voltage V CC = MAX, V I = 7.V 1 µa I IH High-level input current V CC = MAX, V I = 2.7V 2 µa I IL Low-level input current V CC = MAX, V I =.5V 1.2 ma Others V CC = MAX, V I =.5V.6 ma I OS Short-circuit output current NO TAG V CC = MAX 6 15 ma I CC Supply current (total) 4 V CC = MAX ma NOTES: 1. For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio for the applicable type. 2. All typical values are at V CC = 5V, T amb = 25 C. 3. Not more than one output should be shorted at a time. For testing I OS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 4. I CC is measured after applying a momentary 4.5V, then ground to the clock input with all other inputs grounded and all outputs open Jan 5 6

7 AC ELECTRICAL CHARACTERISTICS LIMITS T amb = +25 C T amb = C to +7 C SYMBOL PARAMETER TEST CONDITIONS V CC = +5V V CC = +5V ± 1% UNIT C L = 5pF, R L = 5Ω C L = 5pF, R L = 5Ω MIN TYP MAX MIN MAX f MAX Maximum clock frequency Waveform MHz Propagation delay to Q n (, High or Low) Propagation delay to Propagation delay to Propagation delay to AC SETUP REQUIREMENTS Waveform 1 Waveform 1 Waveform 2 Waveform 3 LIMITS LIMITS T amb = +25 C T amb = C to +7 C SYMBOL PARAMETER TEST CONDITIONS V CC = +5.V V CC = +5.V ± 1% UNIT C L = 5pF, R L = 5Ω C L = 5pF, R L = 5Ω t h (H) t h (L) t h (H) t h (L) t h (H) t h (L) t h (H) t h (L) t w (H) t w (L) Setup time, High or Low D n to Hold time, High or Low D n to Set-up time, High or Low or to Hold time, High or Low or to Set-up time, High or Low to Hold time, High or Low to Set-up time, High or Low to Hold time, High or Low to U or D pulse width, High or Low Waveform 4 Waveform 4 Waveform 5 Waveform 5 Waveform 4 Waveform 4 Waveform 6 Waveform 6 Waveform MIN TYP MIN MAX Jan 5 7

8 AC WAVEFORMS For all waveforms, = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. 1/f MAX t W (H) t W (L) Q n VM SF792 Waveform 2. Propagation Delays Input to Terminal Count Output SF791A Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency D n t s t h t h = t h = n Waveform 3. Propagation Delay Input to Terminal Count Output SF793 Waveform 4. Parallel Data and Parallel Enable Setup and Hold Times SF794 t h (L) t h (H) t h (L) t h (H) n n Q n NO CHANGE COUNT NO CHANGE Q n COUNT DOWN COUNT UP Waveform 5. Count Enable Setup and Hold Times SF795 SF796 Waveform 6. Up/Down Control Setup and Hold Times 1996 Jan 5 8

9 TIMING DIAGRAM (Typical Load, Count, and Inhibit Sequences) D D 1 D 2 D 3 and Q Q 1 Q 2 Q 3 SEQUENCE } LOAD COUNT UP INHIBIT COUNT DOWN SF797 NOTES: The operation of the is similar to the Illustration above. 1. Load (preset) to BCD seven 2. Count up to eight, nine (maximum), zero, one, and two 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven TEST CIRCUIT AND WAVEFORM PULSE GENERATOR V IN V CC D.U.T. V OUT NEGATIVE PULSE 9% 1% t THL ( t f ) t w t TLH ( t r ) 1% 9% AMP (V) V R T C L R L Test Circuit for Totem-Pole Outputs POSITIVE PULSE 1% 9% t TLH ( t r ) t w t THL ( t f ) 9% 1% AMP (V) V DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to Z OUT of pulse generators. family 74F Input Pulse Definition INPUT PULSE REQUIREMENTS amplitude rep. rate t w t TLH t THL 3.V 1.5V 1MHz SF Jan 5 9

10 74F168*, DIP16: plastic dual in-line package; 16 leads (3 mil) SOT38-4 * Discontinued part. Please see the Discontinued Product List in Section 1, page Jan 5 1

11 74F168*, SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT19-1 * Discontinued part. Please see the Discontinued Product List in Section 1, page Jan 5 11

12 74F168*, DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contai the design target or goal specificatio for product development. Specificatio may change in any manner without notice. This data sheet contai preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contai Final Specificatio. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no respoibility or liability for the use of any of these products, conveys no licee or title under any patent, copyright, or mask work right to these products, and makes no representatio or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applicatio that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applicatio will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applicatio do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 349 Sunnyvale, California Telephone Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Date of release: July 1994 Document order number: * Discontinued part. Please see the Discontinued Product List in Section 1, page 21.

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook. INTEGRATED CIRCUITS Supercedes data of 1990 Oct 23 IC15 Data Handbook 1996 Mar 12 FEATURE Industrial temperature range available ( 40 C to +85 C) DESCRIPTION The is a dual positive edge-triggered D-type

More information

INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook

INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook INTEGRATED CIRCUITS 1996 Jan 05 IC15 Data Handbook FEATURES Non-inverting outputs Separate enable for each section Common select inputs See 74F253 for 3-State version PIN CONFIGURATION Ea 1 S1 2 I3a 3

More information

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) INTEGRATED CIRCUITS Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State) 1995 Mar 31 IC15 Data Handbook Philips Semiconductors Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

More information

1-800-831-4242

1-800-831-4242 Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description

More information

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook. 1997 Jun 30 INTEGRATED CIRCUITS IC24 Data Handbook 1997 Jun 30 FEATURES Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5 V CMOS low power consumption

More information

74AC191 Up/Down Counter with Preset and Ripple Clock

74AC191 Up/Down Counter with Preset and Ripple Clock 74AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature

More information

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation

More information

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control August 1986 Revised February 1999 DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control General Description The DM74LS191 circuit is a synchronous, reversible, up/ down counter. Synchronous operation

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS90 is a synchronous UP/DOWN BCD Decade (842) Counter and the SN54/74LS9 is a synchronous UP/DOWN Modulo-6

More information

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY COUNTER WITH ASYNCHRONOUS CLEAR INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED

More information

SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS Single own/ Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Optio Include Plastic Small-Outline

More information

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance

More information

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161

More information

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop Dual D-Type Positive Edge-Triggered Flip-Flop General Description The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is traferred

More information

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. PRESETTABLE BCD/DECADE UP/DOWN COUNTERS PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS The SN54/74LS190 is a synchronous UP/DOWN BCD Decade (8421) Counter and the SN54/74LS191 is a synchronous UP/DOWN Modulo-

More information

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control 54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control General Description This circuit is a synchronous reversible up down counter The 191 is a 4-bit binary counter Synchronous

More information

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS

SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic

More information

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock September 1986 Revised March 2000 DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation

More information

INTEGRATED CIRCUITS. NE558 Quad timer. Product data Supersedes data of 2001 Aug 03. 2003 Feb 14

INTEGRATED CIRCUITS. NE558 Quad timer. Product data Supersedes data of 2001 Aug 03. 2003 Feb 14 INTEGRATED CIRCUITS Supersedes data of 2001 Aug 03 2003 Feb 14 DESCRIPTION The Quad Timers are monolithic timing devices which can be used to produce four independent timing functions. The output sinks

More information

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock 74LS193 Synchronous 4-Bit Binary Counter with Dual Clock General Description The DM74LS193 circuit is a synchronous up/down 4-bit binary counter. Synchronous operation is provided by having all flip-flops

More information

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter 54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting

More information

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register Rev. 10 21 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an (parallel-to-serial converter) with a synchronous serial data input (DS), a clock

More information

74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register

74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 74F675A contai a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial

More information

74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information

74HC377; 74HCT377. 1. General description. 2. Features and benefits. 3. Ordering information Rev. 4 24 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an octal positive-edge triggered D-type flip-flop. The device features clock (CP)

More information

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger Rev. 5 29 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn)

More information

8-bit synchronous binary down counter

8-bit synchronous binary down counter Rev. 5 21 April 2016 Product data sheet 1. General description The is an 8-bit synchronous down counter. It has control inputs for enabling or disabling the clock (CP), for clearing the counter to its

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop Rev. 9 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input

More information

74HC165; 74HCT165. 8-bit parallel-in/serial out shift register

74HC165; 74HCT165. 8-bit parallel-in/serial out shift register Rev. 4 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is an 8-bit serial or parallel-in/serial-out shift register. The device

More information

SN54/74LS192 SN54/74LS193

SN54/74LS192 SN54/74LS193 PRESEABLE BCD/DECADE UP/DOWN COUNER PRESEABLE 4-BI BINARY UP/DOWN COUNER he SN4/74LS2 is an UP/DOWN BCD Decade (842) Counter and the SN4/74LS3 is an UP/DOWN MODULO-6 Binary Counter. Separate Count Up and

More information

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger Rev. 5 30 November 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,

More information

8-bit binary counter with output register; 3-state

8-bit binary counter with output register; 3-state Rev. 3 24 February 2016 Product data sheet 1. General description The is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary

More information

3-to-8 line decoder, demultiplexer with address latches

3-to-8 line decoder, demultiplexer with address latches Rev. 7 29 January 2016 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC

More information

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC393; 74HCT393. Dual 4-bit binary ripple counter Rev. 6 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features

More information

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device

More information

HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate

HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate Rev. 6 10 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NAND gate. The outputs are fully buffered for the highest noise

More information

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

1-of-4 decoder/demultiplexer

1-of-4 decoder/demultiplexer Rev. 6 1 April 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications The contains two 1-of-4 decoders/demultiplexers. Each has two address inputs (na0 and na1, an active

More information

MM74HC174 Hex D-Type Flip-Flops with Clear

MM74HC174 Hex D-Type Flip-Flops with Clear Hex D-Type Flip-Flops with Clear General Description The MM74HC174 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity,

More information

14-stage ripple-carry binary counter/divider and oscillator

14-stage ripple-carry binary counter/divider and oscillator Rev. 8 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a with three oscillator terminals (RS, REXT and CEXT), ten buffered outputs (Q3 to

More information

74HC4040; 74HCT4040. 12-stage binary ripple counter

74HC4040; 74HCT4040. 12-stage binary ripple counter Rev. 5 3 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a with a clock input (CP), an overriding asynchronous master reset

More information

74HC238; 74HCT238. 3-to-8 line decoder/demultiplexer

74HC238; 74HCT238. 3-to-8 line decoder/demultiplexer Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive

More information

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with

More information

CD4013BC Dual D-Type Flip-Flop

CD4013BC Dual D-Type Flip-Flop Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement mode traistors. Each

More information

74HC02; 74HCT02. 1. General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate

74HC02; 74HCT02. 1. General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate Rev. 5 26 November 2015 Product data sheet 1. General description 2. Features and benefits The is a quad 2-input NOR gate. Inputs include clamp diodes. This enables the use of current limiting resistors

More information

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides

More information

MM74C74 Dual D-Type Flip-Flop

MM74C74 Dual D-Type Flip-Flop Dual D-Type Flip-Flop General Description The MM74C74 dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit cotructed with N- and P-channel enhancement traistors. Each flip-flop

More information

74HC138; 74HCT138. 3-to-8 line decoder/demultiplexer; inverting

74HC138; 74HCT138. 3-to-8 line decoder/demultiplexer; inverting Rev. 6 28 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive

More information

Quad 2-input NAND Schmitt trigger

Quad 2-input NAND Schmitt trigger Rev. 9 15 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Applications The is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches

More information

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs 74HC574 Octal D-Type Flip-Flop with 3-STATE Outputs General Description Ordering Code: March 1993 Revised May 2005 The HC574 is an advanced high speed CMOS octal flipflop with 3-STATE output fabricated

More information

74HC154; 74HCT154. 4-to-16 line decoder/demultiplexer

74HC154; 74HCT154. 4-to-16 line decoder/demultiplexer Rev. 7 29 February 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a. It decodes four binary weighted address inputs (A0 to A3) to sixteen mutually

More information

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs

DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs DM9368 7-Segment Decoder/Driver/Latch with Constant Current Source Outputs General Description The DM9368 is a 7-segment decoder driver incorporating input latches and constant current output circuits

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

MM74HC273 Octal D-Type Flip-Flops with Clear

MM74HC273 Octal D-Type Flip-Flops with Clear MM74HC273 Octal D-Type Flip-Flops with Clear General Description The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise

More information

74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information

74HC74; 74HCT74. 1. General description. 2. Features and benefits. 3. Ordering information Rev. 5 3 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS

More information

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock 54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock General Description This circuit is a synchronous up down 4-bit binary counter Synchronous operation is provided by

More information

74AC138 74ACT138 1-of-8 Decoder/Demultiplexer

74AC138 74ACT138 1-of-8 Decoder/Demultiplexer 1-of-8 Decoder/Demultiplexer General Description The AC/ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The

More information

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 7 26 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin

More information

3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.

3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function. Rev. 02 3 September 2007 Product data sheet 1. General description The provides a 3-input EXCLUSIVE-OR function. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of these

More information

MM74HC4538 Dual Retriggerable Monostable Multivibrator

MM74HC4538 Dual Retriggerable Monostable Multivibrator MM74HC4538 Dual Retriggerable Monostable Multivibrator General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature

More information

6-BIT UNIVERSAL UP/DOWN COUNTER

6-BIT UNIVERSAL UP/DOWN COUNTER 6-BIT UNIVERSAL UP/DOWN COUNTER FEATURES DESCRIPTION 550MHz count frequency Extended 100E VEE range of 4.2V to 5.5V Look-ahead-carry input and output Fully synchronous up and down counting Asynchronous

More information

Low-power D-type flip-flop; positive-edge trigger; 3-state

Low-power D-type flip-flop; positive-edge trigger; 3-state Rev. 8 29 November 2012 Product data sheet 1. General description The provides the single D-type flip-flop with 3-state output. The flip-flop will store the state of data input (D) that meet the set-up

More information

The 74LVC1G11 provides a single 3-input AND gate.

The 74LVC1G11 provides a single 3-input AND gate. Rev. 8 17 September 2015 Product data sheet 1. General description The provides a single 3-input AND gate. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

More information

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary General Description This device contains two independent negative-edge-triggered

More information

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised March 2002 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset General Description The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits

More information

74HC573; 74HCT573. 1. General description. 2. Features and benefits. Octal D-type transparent latch; 3-state

74HC573; 74HCT573. 1. General description. 2. Features and benefits. Octal D-type transparent latch; 3-state Rev. 7 4 March 2016 Product data sheet 1. General description The is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE

More information

Low-power configurable multiple function gate

Low-power configurable multiple function gate Rev. 7 10 September 2014 Product data sheet 1. General description The provides configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the

More information

74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger

74AUP1G74. 1. General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger Low-power D-type flip-flop with set and reset; positive-edge trigger Rev. 9 6 January 2014 Product data sheet 1. General description The provides a low-power, low-voltage single positive-edge triggered

More information

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications

74HC595; 74HCT595. 1. General description. 2. Features and benefits. 3. Applications 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 8 25 February 2016 Product data sheet 1. General description The is an 8-bit serial-in/serial or parallel-out shift

More information

HCF4028B BCD TO DECIMAL DECODER

HCF4028B BCD TO DECIMAL DECODER BCD TO DECIMAL DECODER BCD TO DECIMAL DECODING OR BINARY TO OCTAL DECODING HIGH DECODED OUTPUT DRIVE CAPABILITY "POSITIVE LOGIC" INPUTS AND OUTPUTS: DECODED OUTPUTS GO HIGH ON SELECTION MEDIUM SPEED OPERATION

More information

74HC2G02; 74HCT2G02. 1. General description. 2. Features and benefits. 3. Ordering information. Dual 2-input NOR gate

74HC2G02; 74HCT2G02. 1. General description. 2. Features and benefits. 3. Ordering information. Dual 2-input NOR gate Rev. 5 27 September 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input NOR gate. Inputs include clamp diodes. This enables the use of

More information

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop Rev. 8 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. pplications The is a dual -type flip-flop that features independent set-direct input (S), clear-direct input

More information

5495A DM7495 4-Bit Parallel Access Shift Registers

5495A DM7495 4-Bit Parallel Access Shift Registers 5495A DM7495 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel and serial inputs parallel outputs mode control and two clock inputs The registers have three

More information

74HCU04. 1. General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter

74HCU04. 1. General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter Rev. 7 8 December 2015 Product data sheet 1. General description The is a hex unbuffered inverter. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

More information

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset Rev. 9 19 January 2015 Product data sheet 1. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with

More information

X9C102/103/104/503. Terminal Voltages ±5V, 100 Taps. Digitally-Controlled (XDCP) Potentiometer

X9C102/103/104/503. Terminal Voltages ±5V, 100 Taps. Digitally-Controlled (XDCP) Potentiometer APPLICATION NOTE A V A I L A B L E AN20 AN42 53 AN71 AN73 AN88 AN91 92 AN115 Terminal Voltages ±5V, 100 Taps X9C102/103/104/503 Digitally-Controlled (XDCP) Potentiometer FEATURES Solid-State Potentiometer

More information

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate General Description The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits cotructed

More information

CD4013BC Dual D-Type Flip-Flop

CD4013BC Dual D-Type Flip-Flop CD4013BC Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors.

More information

1-Mbit (128K x 8) Static RAM

1-Mbit (128K x 8) Static RAM 1-Mbit (128K x 8) Static RAM Features Pin- and function-compatible with CY7C109B/CY7C1009B High speed t AA = 10 ns Low active power I CC = 80 ma @ 10 ns Low CMOS standby power I SB2 = 3 ma 2.0V Data Retention

More information

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF,

More information

HCF4001B QUAD 2-INPUT NOR GATE

HCF4001B QUAD 2-INPUT NOR GATE QUAD 2-INPUT NOR GATE PROPAGATION DELAY TIME: t PD = 50ns (TYP.) at V DD = 10V C L = 50pF BUFFERED INPUTS AND OUTPUTS STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V

More information

Description. Table 1. Device summary. Order code Temperature range Package Packing Marking

Description. Table 1. Device summary. Order code Temperature range Package Packing Marking 8-bit shift register with output latches (3-state) Applicatio Datasheet - production data SO16 TSSOP16 Automotive Industrial Computer Coumer Features High speed: f MAX = 59 MHz (typ.) at V CC = 6 V Low

More information

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

. MEDIUM SPEED OPERATION - 8MHz (typ.) @ . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE. MEDIUM SPEED OPERATION - 8MHz (typ.) @ CL = 50pF AND DD-SS = 10. MULTI-PACKAGE PARALLEL CLOCKING FOR SYNCHRONOUS HIGH SPEED OUTPUT RES-

More information

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP.

. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. fmax = 48 MHz (TYP. M54/M74HC190 M54/M74HC191 4 BIT SYNCHRONOUS UP/DOWN COUNTERS. HIGH SPEED fmax = 48 MHz (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)

More information

DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving

More information

LOW POWER SCHOTTKY. http://onsemi.com GUARANTEED OPERATING RANGES ORDERING INFORMATION

LOW POWER SCHOTTKY. http://onsemi.com GUARANTEED OPERATING RANGES ORDERING INFORMATION The TTL/MSI SN74LS151 is a high speed 8-input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS151 can be used as a universal function

More information

74AC139 74ACT139 Dual 1-of-4 Decoder/Demultiplexer

74AC139 74ACT139 Dual 1-of-4 Decoder/Demultiplexer Dual 1-of-4 Decoder/Demultiplexer General Description The AC/ACT139 is a high-speed, dual 1-of-4 decoder/ demultiplexer. The device has two independent decoders, each accepting two inputs and providing

More information

Description. Table 1. Device summary. Order code Temperature range Package Packaging Marking

Description. Table 1. Device summary. Order code Temperature range Package Packaging Marking 14-stage ripple carry binary counter/divider and oscillator Applications Automotive Industrial Computer Consumer Description Datasheet - production data Features Medium speed operation Common reset Fully

More information

TS555. Low-power single CMOS timer. Description. Features. The TS555 is a single CMOS timer with very low consumption:

TS555. Low-power single CMOS timer. Description. Features. The TS555 is a single CMOS timer with very low consumption: Low-power single CMOS timer Description Datasheet - production data The TS555 is a single CMOS timer with very low consumption: Features SO8 (plastic micropackage) Pin connections (top view) (I cc(typ)

More information

256K (32K x 8) Static RAM

256K (32K x 8) Static RAM 256K (32K x 8) Static RAM Features High speed: 55 ns and 70 ns Voltage range: 4.5V 5.5V operation Low active power (70 ns, LL version) 275 mw (max.) Low standby power (70 ns, LL version) 28 µw (max.) Easy

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS

More information

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The

More information

SN54HC157, SN74HC157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS

SN54HC157, SN74HC157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SNHC, SNHC QUADRUPLE 2-LINE TO -LINE DATA SELECTORS/MULTIPLEXERS SCLSB DECEMBER 982 REVISED MAY 99 Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers

More information

Hex buffer with open-drain outputs

Hex buffer with open-drain outputs Rev. 5 27 October 20 Product data sheet. General description The provides six non-inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low

More information

DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs General Description The DM74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the

More information

Triple single-pole double-throw analog switch

Triple single-pole double-throw analog switch Rev. 12 25 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Applications 4. Ordering information The is a triple single-pole double-throw (SPDT) analog switch, suitable

More information

LOW POWER SCHOTTKY. http://onsemi.com GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 751B

LOW POWER SCHOTTKY. http://onsemi.com GUARANTEED OPERATING RANGES ORDERING INFORMATION PLASTIC N SUFFIX CASE 648 SOIC D SUFFIX CASE 751B The SN74LS47 are Low Power Schottky BCD to 7-Segment Decoder/ Drivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving

More information

74HC32; 74HCT32. 1. General description. 2. Features and benefits. Quad 2-input OR gate

74HC32; 74HCT32. 1. General description. 2. Features and benefits. Quad 2-input OR gate Rev. 5 4 September 202 Product data sheet. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages

More information

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS. For a complete data sheet, please also download: INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC6 74C/CT/CU/CMOS ogic Family Specifications The IC6 74C/CT/CU/CMOS ogic Package Information The IC6 74C/CT/CU/CMOS ogic

More information