DATA SHEET. HEF40193B MSI 4-bit up/down binary counter. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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1 INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC File under Integrated Circuits, IC04 January 1995

2 DESCRIPTION The is a 4-bit synchronous up/down binary counter. The counter has a count-up clock input (CP U ), a count-down clock input (CP D ), an asynchronous parallel load input (PL), four parallel data inputs (P 0 to P 3 ), an asynchronous master reset input (MR), four counter outputs (O 0 to O 3 ), an active LOW terminal count-up (carry) output (TC U ) and an active LOW terminal count-down (borrow) output (TC D ). The counter outputs change state on the LOW to HIGH transition of either clock input. However, for correct counting, both clock inputs cannot be LOW simultaneously. The outputs TC U and TC D are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH to LOW transition of CP U will cause TC U to go LOW. TC U will stay LOW until CP U goes HIGH again. Likewise, output TC D will go LOW when the circuit is in the zero state and CP D goes LOW. When PL is LOW, the information on P 0 to P 3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop. Fig.2 Pinning diagram. PINNING PL P 0 to P 3 CP U CP D MR TC U TC D O 0 to O 3 Fig.1 Functional diagram. parallel load input (active LOW) parallel data inputs count-up clock pulse input (LOW to HIGH, edge-triggered) count-down clock pulse input (LOW to HIGH, edge-triggered) master reset input (asynchronous) buffered terminal count-up (carry) output (active LOW) buffered terminal count-down (borrow) output (active LOW) buffered counter outputs P(N): 16-lead DIL; plastic (SOT38-1) D(F): 16-lead DIL; ceramic (cerdip) (SOT74) T(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, I DD LIMITS category See Family Specification January

3 Fig.3 Logic diagram (continued on Fig.4). January

4 Fig.4 Logic diagram (continued from Fig.3). January

5 FUNCTION TABLE MR PL CP U CP D MODE H X X X reset (asyn.) L L X X parallel load L H H count-up Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition L H H count-down Logic equations for terminal count: TC U = O 0 O 1 O 2 O 3 CP U TC D = O 0 O 1 O 2 O 3 CP D Fig.5 State diagram. AC CHARACTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns V DD V TYPICAL FORMULA FOR P (µw) Dynamic power f i + (f o C L ) V 2 DD where dissipation per f i + (f o C L ) V 2 DD f i = input freq. (MHz) package (P) f i + (f o C L ) V 2 DD f o = output freq. (MHz) C L = load capacitance (pf) (f o C L ) = sum of outputs V DD = supply voltage (V) January

6 AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays CP U O n ns 183 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 74 ns + (0,23 ns/pf) C L ns 52 ns + (0,16 ns/pf) C L ns 143 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 59 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L CP D O n ns 183 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 74 ns + (0,23 ns/pf) C L ns 57 ns + (0,16 ns/pf) C L ns 143 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 59 ns + (0,23 ns/pf) C L ns 42 ns + (0,16 ns/pf) C L CP U TC U ns 98 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 39 ns + (0,23 ns/pf) C L ns 27 ns + (0,16 ns/pf) C L ns 68 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 29 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L CP D TC D ns 113 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 44 ns + (0,23 ns/pf) C L ns 32 ns + (0,16 ns/pf) C L ns 73 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 29 ns + (0,23 ns/pf) C L ns 22 ns + (0,16 ns/pf) C L MR O n ns 168 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 69 ns + (0,23 ns/pf) C L ns 52 ns + (0,16 ns/pf) C L MR TC U ns 118 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 49 ns + (0,23 ns/pf) C L ns 37 ns + (0,16 ns/pf) C L MR TC D ns 338 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 119 ns + (0,23 ns/pf) C L ns 92 ns + (0,16 ns/pf) C L PL O n ns 158 ns + (0,55 ns/pf) C L HIGH to LOW 10 t PHL ns 64 ns + (0,23 ns/pf) C L ns 47 ns + (0,16 ns/pf) C L January

7 V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA ns 118 ns + (0,55 ns/pf) C L LOW to HIGH 10 t PLH ns 49 ns + (0,23 ns/pf) C L ns 37 ns + (0,16 ns/pf) C L AC CHARACTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns V DD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Output transition times ns 10 ns + (1,0 ns/pf) C L HIGH to LOW 10 t THL ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L ns 10 ns + (1,0 ns/pf) C L LOW to HIGH 10 t TLH ns 9 ns + (0,42 ns/pf) C L ns 6 ns + (0,28 ns/pf) C L Set-up time ns P n PL 10 t su ns ns Hold time ns P n PL 10 t hold 5 25 ns ns Minimum CP U or CP D ns pulse width; LOW 10 t WCPL ns ns Minimum MR ns pulse width; HIGH 10 t WMRH ns ns Minimum PL ns pulse width; LOW 10 t WPLL ns ns Recovery time ns for MR 10 t RMR ns ns Recovery time ns for PL 10 t RPL ns ns Maximum clock 5 2,5 5 MHz pulse frequency 10 f max 7 14 MHz MHz see also waveforms Fig.6 January

8 Fig.6 Waveforms showing recovery times for PL and MR, minimum pulse widths for CP U,CP D,PL and MR, and set-up and hold times for P to PL. Set-up times and hold times are shown as positive values but may be specified as negative values. January

9 Fig.7 Timing diagram. APPLICATION INFORMATION Some examples of applications for the are: Up/down difference counting Multistage ripple counting Multistage synchronous counting Fig.8 Example of cascaded ICs. January

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