Design: a mod8 Counter


 Dominic Parker
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1 Design: a mod8 Counter A mod8 counter stores a integer value, and increments that value (say) on each clock tick, and wraps around to 0 if the previous stored value was 7. So, the stored value follows a cycle:
2 Design: State Machine 2 We need eight different states for our counter, one for each value from 0 to 7. We can describe the operation by drawing a state machine. The nodes represent states and the edges represent transitions and are labeled with the input (clock in this case) that causes the transition to occur
3 Design: State Table 3 A state table summarizes the state machine and is useful in deriving equations later: Current State Input Next State
4 Design: Deriving Equations We will derive an equation for each of the next state functions: Current State Input Next State C2 C C0 N2 N N N0= C2 C C0+ C2 C C0+ C2 C C0+ C2 C C0= C0 4 N= C2 C C0+ C2 C C0+ C2 C C0+ C2 C C0= C C0+ C C0 N 2= C2 C C0+ C2 C C0+ C2 C C0+ C2 C C0 = C2 C C0+ C2 C+ C2 C0
5 Design: Mapping to D Flipflops 5 Since each state is represented by a 3bit integer, we can represent the states by using a collection of three flipflops (moreorless a miniregister). We will implement the circuit using D flipflops, which make for a simple translation from the state table because a D flipflop simply accepts its input value. D Q ~Q So, we just need to feed each of the flipflops the value of the appropriate nextstate function equation derived earlier
6 D Flipflop 6 The D flipflop takes one data input and updates its state Q, on a clock tick, according to the table: D Q ~Q D CK Q ~Q In the following Logisim diagrams, the D flipflops update state on the falling edge (when the clock goes from high to low).
7 JK Flipflop 7 The JK flipflop takes two data inputs and updates its state Q, on a clock tick, according to the table: J K Q ~Q no change opposite J K CK Q ~Q In the following Logisim diagrams, the JK flipflops update state on the falling edge (when the clock goes from high to low).
8 Implementation 8 N 2= C2 C C0+ C2 C+ C2 C0 N= C C0+ C C0 N0= C0
9 Design: Mapping to JK Flipflops We could also implement the circuit using JK flipflops. 9 J K Q ~Q no change opposite This will require a little more effort, since the inputs to the JK flipflops cannot merely be set to equal the next state functions.
10 Design: Deriving JK Inputs 0 We must examine each current/next state pair and determine how/if the relevant flipflop needs to change state: Flipflop Inputs Current State Next State J2 K2 J K J0 K For this simple circuit, we either want the JK flipflop to hold state (both inputs 0) or to toggle state (both inputs ).
11 Design: Deriving JK Input Equations We can derive equations in the usual manner from the previous table: J 0= K0= Flipflop Inputs Current State J2 K2 J K J0 K0 C2 C C J= K= C2 C C0+ C2 C C0+ C2 C C0+ C2 C C0 = C0 J 2= K 2= C2 C C0+ C2 C C0= C C0
12 Implementation 2 J= K= C0 J 2= K 2= C C0 J 0= K0=
13 A mod6 Counter 3 We can use JK flipflops to implement a 4bit counter: Note that the J and K inputs are all set to the fixed value, so the flipflops "toggle". As the clock signal runs, the circuit will cycle its outputs through the values 0000, 000, 000,..., and then repeat the pattern. So, it counts clock ticks, modulo 6.
14 mod6 Counter: first tick 4 Suppose the counter is in the initial state shown below (output is 0000). When the clock cycles from high to low:  the rightmost sees its (inverted) clock signal go from low to high, and so it toggles its state to  the next flipflop sees its clock signal go from high to low, and so it doesn't toggle  and so, neither do the other flipflops So, the output is 000:
15 mod6 Counter: second tick 5 Suppose the counter is now in the state shown below (output is 000). When the clock cycles from high to low (2 nd cycle):  the rightmost sees its (inverted) clock signal go from low to high, and so it toggles its state to 0  the next flipflop sees its clock signal go from low to high, and so it toggles its state to  the next flipflop sees its clock signal go from high to low, so it doesn't toggle So the output is 000.
16 mod6 Counter: third tick 6 Suppose the counter is now in the state shown below (output is 000). When the clock cycles from high to low (3rd cycle):  the rightmost sees its (inverted) clock signal go from low to high, and so it toggles its state to  the next flipflop sees its clock signal go from high to low, and so it doesn't toggle So the output is 00.
17 mod6 Counter: fourth tick 7 Suppose the counter is now in the state shown below (output is 00). When the clock cycles from high to low (4th cycle):  the rightmost sees its (inverted) clock signal go from low to high, and so it toggles its state to 0  the next flipflop sees its clock signal go from low to high, and so it toggles its state to 0  the next flipflop sees its clock signal go from low to high, and so it toggles its state to So the output is 000.
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