exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576
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1 exclusive-or and Binary Adder R eouven Elbaz reouven@uwaterloo.ca Office room: DC3576
2 Outline exclusive OR gate (XOR) Definition Properties Examples of Applications Odd Function Parity Generation and Checking Binary Adder Half adder Full adder Binary ripple carry adder Carry lookahead generator
3 exclusive-or or XOR The exclusive-or operation is denoted by the symbol: a b = ab + a b a b XOR Gate Symbol:
4 XOR properties a 0 = a a 1 = a a a = 0 a a = 1 a b = a b = (a b) Commutative: a b = b a Associative operation: (a b) c = (a c) b = (b c) a At home: show the Commutative and Associative properties by replacing the XOR by its equivalent Boolean expression.
5 2-input XOR gate construction 1 st solution: using AND-OR-NOT gates x y 2 nd solution: using NAND x y
6 Odd Function An odd function detects an odd number of one in an n-bit word. An n-variable exclusive-or operation requires an odd number of variables set to 1 to be evaluated as true ( 1 ) ). Ex: f = a b c a b c f
7 3-input Odd Function a f= a b c = (ab + a b)c + (ab + a b) c = ab c + a bc + (a +b)(a+b )c = ab c + a bc + a b c + abc bc m m m m m m 4 m 1 m 5 m 3 m 7 m 2 m 6 3-input Even Function: An Even function is true (= 1 ) when it has an even number of 1 as inputs.
8 Parity Generation and Checking A Parity bit (P) is used to detect errors during transmission of binary information. A parity bit is added to a message to be transmitted to make the number of 1 in the message either even (even parity bit) ) or odd (odd parity bit). Parity generator: circuit that generates the parity bit at the transmitter end. Parity checker: circuit that verifies the parity bit at the receiver end. How to construct a Parity generator that generates an even parity bit?
9 Parity generator (even parity bit) The even parity bit must be added to the 3-bit message to make the number of 1 even P= 1 when the number of 1 in the original message is odd. P= a b c Odd function 3-bit message Parity bit a b c P How to construct a Parity checker that verifies the parity?
10 Parity checker How many input bits? 4: the 3-bit message and P When is C (output of the parity checker) evaluated to 1? when the number of 1 at its inputs is odd C= a b c P Odd function How to implement a Parity generator with a Parity checker circuit? Setting P= 0 in the Parity checker circuit provides us with a parity generator (since c 0=c)
11 Outline exclusive OR gate (XOR) Definition Properties Examples of Applications Odd Function Parity Generation and Checking Binary Adder Half adder Full adder Binary ripple carry adder Carry lookahead generator
12 Binary Adder A Binary Adder circuit produces the sum of two n-bit words. Example: Binary addition of two 4-bit words A and B: A = 1011 and B = 0011 S=A+B= 1110 Input carry A 1011 B S 0 Output carry Two kind of operations: addition of 2 bits and addition of 3 bits (augend and addend bits and the previous carry)
13 Half Adder A Half Adder circuit produces the sum of 2 binary bits and the corresponding carry: S = a b C = ab a b c s
14 Full Adder (1/2) a b C A Full Adder circuit produces the sum in C out S of 3 binary bits and outputs a carry a a bc in Karnaugh map for S S=ab C in +a b C in +abc in +a bc in bc in Karnaugh map for C C out =ac in +bc in +ab
15 Full adder (2/2) S is an odd function of the 3 input bits S = a b C in C out = ab C in + ab C in + ab C in + a b C in = ab + C in (ab + a b) = ab + C in (a b) a b C in C out S Half Adder Half Adder a b OR C out Full Adder C in Full Adder 2 Half Adders and 1 OR gate S
16 Binary Adder circuit Example: Binary addition of two 4-bit words A and B: A = 1011 and B = 0011 S=A+B= A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 C 4 Full C 3 Full C 2 Full C 1 Full 0 Adder 0 Adder 1 Adder 1 Adder 0 C 0 S 3 S 2 S 1 S The carries are connected in chain through the full adders Binary ripple carry adder For a n-bit ripple carry adder, the longest propagation delay for S to For a n bit ripple carry adder, the longest propagation delay for S n to settle to its steady-state is defined by the propagation of C 0 to C n : 2n level of gates.
17 Binary ripple carry adder A 3 B 3 A 2 B 2 A 1 B 1 A 0 B 0 C 4 Full Adder C 3 Full Adder C 2 Full Adder C 1 Full Adder C 0 S 3 S 2 S 1 S 0 2n level of gates 4-bit binary adder: 8 level of gates
18 Carry Lookahead Generator Lets define two binary variables depending on inputs only: The carry propagate: P i = A i B i The carry generate: G i = A i B i S i =P i C i C i+1 = P i C i + G i 4-bit binary adder: C 0 = Input carry C 1 = G 0 +P 0 C 0 C 2 = G 1 +P 1 C 1 = G 1 + P 1 G 0 + P 1 P 0 C 0 C 3 = G 2 +P 2 C 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C 0 C 4 = G 3 +P 3 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0
19 Carry Lookahead Generator
20 Binary Adder with Carry Lookahead The outputs S1 to S3 have equal propagation delay times. The #of levels of gates is constant for any pair of bits to add: 4
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