Digital Fundamentals. Lab 8 Asynchronous Counter Applications


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1 Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003). Horne Rev. 2 (1/2008). Bradbury Digital Fundamentals CETT 1425 Lab 8 Asynchronous Counter Applications Name: Date: Objectives: To construct and evaluate a 1 counter built from a 74LS293 IC Decade and 4Bit Binary Counters To develop a block diagram for a 24hour digital clock. To design, construct, and evaluate a 24hour clock. Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci Equipment: Circuit simulator (MultiSIM or an equivalent) Introduction: 74LS293 is an asynchronous ripple counter. Each device provides circuitry for a 3bit counter, 4bit counter, or divide by 2 circuit. The block and logic diagrams are shown in the following figures. CB VCC CA RO1 RO2 D (MSB) C B A (LSB) 74LS293 Block Diagram Page 1 of
2 CA RO1 RO2 CB, inputs tied to VCC internally A (LSB) B C D (MSB) Logic Diagram for 74LS293 The 74LS293 has four  flipflops with outputs A, B, C, and D, where A is the LSB and D is the MSB. Each flipflop has an asynchronous activelow CLEAR line that is connected to the output of a 2input NAND gate. The NAND gate is used to create counters with a number less than the maximum (2 N ). Flipflops B, C, and D are connected as a 3bit ripple counter. Flipflop A is not connected to the other flipflops and can be used as a single dividebytwo circuit. There are clock inputs for both A and the 3bit counter circuit. If a counter with a number greater than 8 is required, the output A can be connected externally to CB input to create a 4bit ripple counter circuit. In this case, only the CA input is the clock for the circuit. If a counter requires more than 2 of the outputs to be connected to the NAND gate, an external AND gate must be added to one of the NAND gate inputs. Counters with a number larger than 1 can be created by cascading 74LS293 counters. The number is equal to the product of the individual numbers. For example, a 80 counter can be implemented as shown in the following figure (general block diagram, all of the wiring is not shown). 8 D Page 2 of
3 Procedure: 1. Construct the following 1 counter in MultiSIM. Note that the output A is tied to the CB clock input through an inverter to implement a 4bit ripple counter. [The inverter is required due to a model error in the Multisim simulation. The CB model input is not NGT as the schematic symbol implies. The inverter must be used in your subsequent counter designs.] U3 DCD_HEX VCC 5V U1 9 A A 5 11 B B 4 8 C R0(1) 13 D R0(2) 74LS293N 1 ey = Space 2. Record the display value for each clock (falling edge) in the following table. Clock Display Value Page 3 of
4 3. What outputs must be connected to the NAND gate inputs (R01 & R02) to create a counter? R01 = R02 = 4. Modify the circuit and simulate to verify the circuit operates as a counter. 5. Add a counter by copying the and changing its R01/R02 connections. You can skip the isolated first stage of the 74LS293 and build the counter from the three upper bit flipflops. An inverter will still be necessary on the CB input. Input 4 of the hex display must be grounded for stage. Simulate to verify the circuit operates as a counter. 74LS293N for CA RO1 RO2 CB A (LSB) B C D (MSB) TO R02 TO R01. The following is a general block diagram for a digital clock. A 24hour clock is to be designed using 5 counters plus a single flipflop. Label the # for each of the counter blocks shown to produce a 24 hour clock. AM/PM Hours Section Minutes Section Seconds Section 2 7. Implement the 24hour clock in MultiSIM or an equivalent circuit simulator using 74LS293 ICs. Use 7segment displays (demonstrated in procedure 1 & 3) to display the time. Use a LED probe to indicate AM and PM. Use a 5V, 1kHz output clock generator from the AC source menu box (upper right). 8. The counter should display counts of 1 to (hex C). The counter you build will count from 0 to 11 (hex B). Run the counter output bits through a 74HC283N4V full adder with the B inputs grounded and the carryin set to Vcc. The sum bits will attach to the hex display. This will add 1 so that the display works correctly. 9. The AM/PM flipflop (PGT generic typed wired to toggle) should be clocked when the display changes from 11 to since AM begins at midnight and PM begins at noon. Since the Page 4 of
5 counter 11 (11) corresponds to the display due to the adder, use an AND gate to decode the 11 to provide the rising edge to trigger the AM/PM flipflop.. It is quicker to run two identical 0 counters from the same clock instead of waiting for the seconds to trigger the minutes. Also run the + AM/PM directly from the clock to save time. Label the schematic so that each section (seconds, minutes, hours, etc.) and number of each counter can be clearly identified. Demonstrate the operation of the circuit to your instructor, when approved print a copy of the schematic. ATTACH A COPY OF THE MULTISIM SCHEMATIC TO THE LAB. AM/PM Hours Section Minutes Section Seconds Section 2 1 Hz CLOC Page 5 of
6 Review uestions: Answer the following questions after the lab is completed. 1. What is the advantage of using a 74LS293 component versus constructing a 1 counter out of discrete  flipflops? 2. What is the largest counter that can be implemented by cascading two 74LS293 components together? 3. What is the number of the 74LS293 circuit shown below? VCC 5V U1 9 A A 5 11 B B 4 8 C R0(1) 13 D R0(2) 74LS293N 1 ey = Space Page of
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